Process and system for routing interconnections between logic system elements

Claim 2

In a process for producing circuit artwork by a data processing machine from coded information of a logic system wherein the data processor generates data representing packages of the logic system elements, assigns locations to the packaged elements, routes the interconnections between terminal pins of the packaged logic system elements and produces instructions for operating a data plotter to generate the circuit artwork, the steps in the routing routine of: identifying signatures between terminal pins of the logic system elements and coding the coordinates of the terminal pin locations, establishing bounding limits within which a numbered ordered maze will be developed, developing a numbered ordered maze within the predetermined bounding limits from a starting pin to a destination pin for an interconnection, and backtracking through the ordered maze to generate a representation of an interconnection between a start pin and a destination pin.

Claim 3

A process for producing circuit artwork by a data processing machine as set forth in claim 1 including repeating the steps of: developing a numbered ordered maze within the predetermined bounding limits from a starting pin to a destination pin for each interconnection in the logic system, and backtracking through the ordered maze for each intErconnection to generate a representation of a connecting path between a start pin and a destination pin.

Claim 4

A process for producing circuit artwork by a data processing machine as set forth in claim 1 including the step of assigning each path generated by the backtracking routine to a defined equivalence class.

Claim 5

A process for producing circuit artwork by a data processing machine as set forth in claim 1 where the numbered ordered maze is developed from multiple starting points and proceeds to multiple destination points.

Claim 6

A process for producing circuit artwork by a data processing machine set forth in claim 1 wherein the numbered ordered maze is developed from multiple start points to a single destination point.

Claim 7

A process for producing circuit artwork by a data processing machine as set forth in claim 1 wherein backtracking through the ordered maze proceeds along channel priorities read into the data processor as input data.

Claim 8

A process for producing artwork by a data processing machine as set forth in claim 6 wherein the backtracking routine proceeds in the direction of the highest priority, if equal priorities are present the backtracking will proceed in a direction resulting in the fewest number of turns.

Claim 9

A process for producing circuit artwork by a data processing machine as set forth in claim 7 wherein the backtracking routine will proceed in a direction resulting in the fewest turns if the current priority is greater than any surrounding priorities.

Claim 10

In a process for producing circuit artwork by a data processing machine from coded information of a logic system wherein the data processor generates data representing packages of the logic system elements, assigns locations to the packaged elements, routes the interconnections between terminal pins of the packaged logic system elements and produces instructions for operating a data plotter to generate the circuit artwork, the steps in the routing routine of: identifying signatures between terminal pins of the logic elements circuit elements and coding the coordinates of the terminal pin locations, computing an interconnection order for each of the identified signatures between terminal pin locations, developing a numbered ordered maze from a starting pin to a destination pin for the next interconnection in the computed order within bounding limits that restrict an interconnection to mutually substantially perpendicular sections, backtracking through the ordered maze to generate a representation of an interconnecting path between a start pin and a destination pin, developing a second numbered ordered maze from a starting pin to a destination pin for the next interconnection available in the computed order within predetermined bounding limits that restrict the interconnection to an area within a rectangle having the starting pin and destination pin at opposite corners thereof, backtracking through the second ordered maze to generate a representation of an interconnecting path between a start pin and a destination pin, developing a third ordered numbered maze from a starting pin to a destination pin for the next interconnection available in the computed order within predetermined bounding limits outlined by a rectangle defined by input data, and backtracking through the third numbered ordered maze to generate a representation of an interconnecting path between a start pin and a destination pin.

Claim 11

In a process for producing circuit artwork by a data processing machine from coded information of a logic system wherein the data processor generates data representing packages of the logic system elements, assigns locations to the packaged elements, routes the interconnections between terminal pins of the packaged logic system elements and produces instructions for operating a data plotter to generate the circuit artwork, the steps in the routing routine of: identifying signatures between terminal pins of the logic elements circuit elements and coding the coordinates of the terminal pin locations, computing an interconnection order for each of the identified signatures between terminal pin locations, developing a numbered ordered maze from a starting pin to a destination pin for the next interconnection in the computed order within bounding limits that restrict an interconnection to mutually substantially perpendicular sections, backtracking through the ordered maze to generate a representation of an interconnecting path between a start pin and a destination pin, developing a second numbered ordered maze from a starting pin to a destination pin for the next interconnection available in the computed order within predetermined bounding limits that restrict the interconnection to an area within a rectangle having the starting pin and destination pin at opposite corners thereof, backtracking through the second ordered maze to generate a representation of an interconnecting path between a start pin and a destination pin, developing a third ordered numbered maze from a starting pin to a destination pin for the next interconnection available in the computed order within predetermined bounding limits outlined by a rectangle defined by input data, and backtracking through the third numbered ordered maze to generate a representation of an interconnecting path between a start pin and a destination pin.

Claim 12

A process for producing circuit artwork by a data processing machine as set forth in claim 9 repeating the steps of: developing a numbered ordered maze from a starting pin to a destination pin for each of the interconnections in the computed order within the bounding limits that restrict an interconnection to mutually substantially perpendicular sections prior to developing the second and third numbered ordered maze, and backtracking through the ordered maze for each of the interconnections to generate a representation of a connecting path beTween a start pin and a destination pin prior to developing the second and third numbered ordered maze.

Claim 13

A process for producing circuit artwork by a data processing machine as set forth in claim 10 including repeating the steps of: developing the second numbered ordered maze from a start pin to a destination pin for each of the interconnections remaining in the computed order prior to developing the third numbered ordered maze, and backtracking through the second numbered ordered maze for each interconnection to generate a representation of a connecting path between a start pin and a destination pin prior to developing the third numbered ordered maze.

Claim 14

A process for producing circuit artwork by a data processing machine as set forth in claim 11 including repeating the steps of: developing the third numbered ordered maze from a start pin to a destination pin for each of the remaining interconnections in the computed order, and backtracking through the third numbered ordered maze for each interconnection to generate a representation of a connecting path between the start pin and a destination pin.

Claim 15

A process for producing circuit artwork by a data processing machine as set forth in claim 12 including repeating developing the first, second and third numbered ordered maze for each interconnection remaining in the computed order after the first sequence thereof, and expanding the bounding limits to include additional area of the circuit board configuration.

Claim 16

A process for producing circuit artwork by a data processing machine as set forth in claim 13 wherein the backtracking through the ordered maze proceeds along channel priorities read into the data processor as input data.

Claim 17

A process for producing circuit artwork by a data processing machine as set forth in claim 14 wherein the backtracking through each ordered maze proceeds along channel priorities with the general restriction that the interconnecting path turns as few times as possible.

Claim 18

A process for producing circuit artwork by a data processing machine as set forth in claim 9, including the steps of: defining the location and parameters of an input/output connector, establishing bounding limits within which a numbered ordered maze will be developed, identifying signatures on the connector pins within the bounding limits with terminal pin signatures, developing a numbered ordered maze from a terminal pin signature to an input/output connector signature within bounding limits that restrict an interconnection to a rectangular area that includes the terminal pin start point and the connector pins as destination points, and backtracking through the ordered maze to generate a representation of an interconnecting path between a terminal pin and one input/output connector pin.

Claim 19

A process for producing circuit artwork by a data processing machine as set forth in claim 16, including repeating the steps of: developing a numbered ordered maze for each terminal pin signature identified with input/output connector pins within the established bounding limits, and backtracking through the ordered maze for each signature to generate a representation of a connecting path to a connector pin.

Claim 20

In a process for producing circuit artwork by a data processing machine from coded information of a logic system wherein the data processor generates data representing packages of the logic system elements, assigns locations to the packaged elements, routes the interconnections between terminal pins of the packaged logic system elements and produces instructions for operating a data plotter to generate the circuit artwork, the steps in the routing routine of: identifying signatures between terminal pins of the logic system elements and coding the coordinates of the terminal pin locations, establishing bounding limits within which a numbered ordered maze will be developed, developing a numbered ordered maze foR the next interconnection available from a starting pin to a destination pin within the predetermined bounding limits, and backtracking through the ordered maze along channel priorities to generate a representation of an interconnecting path between a start pin and a destination pin.

Claim 21

In a process for producing circuit artwork by a data processing machine from coded information of a logic system wherein the data processor generates data representing packages of the logic system elements, assigns locations to the packaged elements, routes the interconnections between terminal pins of the packaged logic system elements and produces instructions for operating a data plotter to generate the circuit artwork, the steps in the routing routine of: identifying signatures between terminal pins of the logic system elements and coding the coordinates of the terminal pin locations, establishing bounding limits within which a numbered ordered maze will be developed, developing a numbered ordered maze foR the next interconnection available from a starting pin to a destination pin within the predetermined bounding limits, and backtracking through the ordered maze along channel priorities to generate a representation of an interconnecting path between a start pin and a destination pin.

Claim 22

A process for producing circuit artwork by a data processing machine as set forth in claim 18 wherein the circuit board configuration is divided into cells along vertical and horizontal channels and each cell is coded with a priority number one through nine to establish the channel priorities.

Claim 23

A process for producing circuit artwork by a data processing machine as set forth in claim 19 wherein the channel priority for each cell on the circuit board configuration is determined by the sum of the channel priorities of the intersecting vertical and horizontal channels.

Claim 24

A process for producing circuit artwork by a data processing machine as set forth in claim 20 wherein the backtracking proceeds to the highest numbered channel priority greater than the priority of the cell presently considered.

Claim 25

A process for producing circuit artwork by a data processing machine as set forth in claim 21 wherein the backtracking proceeds along a straight line when the channel priorities of the surrounding cell are less than the cell presently under consideration.