High-density wirebond chip interconnect for multi-chip modules

Claim 2

A multi-chip module comprising: a substrate having an die mounting surface formed thereon; patterned metallization formed on the die mounting surface of the substrate to provide a plurality of ground conductors and a plurality of power supply conductors; a first integrated circuit (IC) mounted to the patterned metallization of the die mounting surface; a first row of bond pads formed on an upper surface periphery of the first IC; a second row of bond pads formed on the upper surface periphery of the first IC and inside the first row of bond pads; a second IC mounted to the die mounting surface; a third row of bond pads formed on an upper surface periphery of the second IC; a fourth row of bond pads formed on the upper surface periphery of the second IC and inside the third row of bond pads; a first set of wire bonds above the substrate coupling the second row of bond pads to the fourth row of bond pads; a second set of wire bonds above the substrate coupling selected ones of the first row of bond pads to selected ones of the third row of bond pads; a third set of wire bonds above the substrate exclusive of the second set of wire bonds coupling selected ones of the first row of bond pads to the patterned metallization formed on the substrate; and a fourth set of wire bonds above the substrate exclusive of the second set of wire bonds coupling selected ones of the third row of bond pads to the patterned metallization formed on the substrate.

Claim 3

The multi-chip module of claim 1 wherein the first, second, third, and fourth rows of bond pads are substantially coplanar.

Claim 4

The multi-chip module of claim 1 wherein the first set of wire bonds has a loop height greater than the second set of wire bonds.

Claim 5

The multi-chip module of claim 1 wherein the first set of wire bonds has a loop height greater than both the second set of wire bonds and the third set of wire bonds.

Claim 6

The multi-chip module of claim 1 wherein the first row of bond pads is staggered from the second row of bond pads and the third row of bond pads is staggered from the fourth row of bond pads.

Claim 7

A multi-chip module comprising: a multi-layer substrate; a patterned metallization layer formed on each layer of the substrate; a multi-tiered cavity formed in the substrate by removing portions of less than all of the layers of the multi-layer substrate, wherein each tier exposes a portion of the patterned metallization layer on a single layer of the substrate; an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity; a plurality of ICs mounted on the IC mounting surface of the cavity; a first set of wire bonds extending from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity; a second set of wire bonds extending from the at least one IC to bond pads of an adjacent IC; and a third set of wire bonds extending from the at least one IC to bond pads of the adjacent IC wherein the third set of wire bonds has a higher loop height than the second set of wire bonds thereby allowing the third set to clear the second set.

Claim 8

A multi-chip module comprising: a multi-layer substrate; a patterned metallization layer formed on each layer of the substrate; a multi-tiered cavity formed in the substrate by removing portions of less than all of the layers of the multi-layer substrate, wherein each tier exposes a portion of the patterned metallization layer on a single layer of the substrate; an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity; a plurality of ICs mounted on the IC mounting surface of the cavity; a first set of wire bonds extending from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity; a second set of wire bonds extending from the at least one IC to bond pads of an adjacent IC; and a third set of wire bonds extending from the at least one IC to bond pads of the adjacent IC wherein the third set of wire bonds has a higher loop height than the second set of wire bonds thereby allowing the third set to clear the second set.

Claim 9

The multi-chip module of claim 6 wherein the first set of wire bonds comprises: a first wire bond extending from at least one IC to bond pads exposed in the patterned metallization of a first tier of the multi-tiered cavity; a second wire bond extending from the at least one IC to bond pads exposed in the patterned metallization of a second tier of the multi-tiered cavity; a third wire bond extending from the at least one IC to bond pads exposed in the patterned metallization of a third tier of the multi-tiered cavity; and a fourth wire bond extending from the a least one IC to bond pads of a fourth tier of the multi-tiered cavity.

Claim 10

The multi-chip module of claim 6 wherein the second and third sets of wire bonds are on the same side of the at least one IC.

Claim 11

The multi-chip module of claim 6 wherein each of the third set of wire bonds is longer than each of the second set of wire bonds.

Claim 12

An electronic circuit comprising: a plurality of integrated circuits (ICs) having four edges and each further including: (a) external input/output circuitry formed on a first edge of the IC; (b) a first type of inter-chip I/O circuitry formed on a second edge opposite of the first edge of the IC; (c) a second type of inter-chip I/O circuitry formed on third and fourth edges of the IC; and a substrate mounted to each of the plurality of integrated circuits such that the first type of inter-chip I/O on each of the plurality of ICs faces the first type of inter-chip I/O of an adjacent one of the plurality of ICs and at least one of the second type of inter-chip I/O faces the second type of inter-chip I/O of an adjacent IC.

Claim 13

An electronic circuit comprising: a plurality of integrated circuits (ICs) having four edges and each further including: (a) external input/output circuitry formed on a first edge of the IC; (b) a first type of inter-chip I/O circuitry formed on a second edge opposite of the first edge of the IC; (c) a second type of inter-chip I/O circuitry formed on third and fourth edges of the IC; and a substrate mounted to each of the plurality of integrated circuits such that the first type of inter-chip I/O on each of the plurality of ICs faces the first type of inter-chip I/O of an adjacent one of the plurality of ICs and at least one of the second type of inter-chip I/O faces the second type of inter-chip I/O of an adjacent IC.

Claim 14

The electronic circuit of claim 10 wherein the first type of inter-chip I/O circuitry further comprises: a first row of bond pads formed on the second edge of the IC and coupled to internal circuitry on the IC; a second row of bond pads formed on the second edge and inside the first row of bond pads and coupled to internal circuitry on the IC, wherein the second row is staggered with respect to the first row of bond pads; a first set of wire bonds coupling some of the first row of bond pads of each IC to selected ones of bond pads of an adjacent IC; a second set of wire bonds coupling each of the second row of bond pads to each of the second row of bond pads of the adjacent IC a first row of bond pads formed on the third edge of the IC and coupled to internal circuitry on the IC; a second row of bond pads formed on the third edge and inside the first row of bond pads and coupled to internal circuitry on the IC, wherein the second row is staggered with respect to the first row of bond pads; a third row of bond pads formed on the fourth edge of the IC and coupled to internal circuitry on the IC; a fourth row of bond pads formed on the fourth edge and inside the third row of bond pads and coupled to internal circuitry on the IC, wherein the fourth row is staggered with respect to the third row of bond pads; first set of wire bonds coupling some of the first row of bond pads of each IC to selected ones of the third row of bond pads of the adjacent IC; and a second set of wire bonds coupling each of the second row of bond pads to each of the fourth row of bond pads of the adjacent IC.

Claim 17

The method of claim 12 wherein the step of forming second wire bonds is performed after the step of forming first wire bond and the step of forming third wire bonds is formed after the step of forming second wire bonds.

Claim 18

The method of claim 13 further comprising the steps of: visually and electrically inspecting the wire bonds before the step of forming the second wire bonds to detect any defective ones of the wire bonds; and repairing at least some of the defective ones of the wire bonds before the step of forming the second wire bonds.

Claim 19

The method of claim 14 further comprising the steps of: inspecting the wire bonds before the step of forming the third wire bonds to detect any defective ones of the wire bonds; and repairing at least some of the defective ones of the wire bonds before the step of forming the third wire bonds.