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Patent US6096642A successfully refreshed from Google Patents.
US6096642A
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Method of forming self-aligned silicide in integrated circuit without causing bridging effects
Assignee: United Microelectronics Corp
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Filing: 1998-08-17
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Granted: 2000-08-01
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Expires: 2018-08-17
Abstract
Abstract A method is provided for forming self-aligned silicide in integrated circuit, which can help prevent the occurrence of a bridging effect in the integrated circuit. This method is characterized in the provision of an elevated spacer structure that can act like a barrier to prevent the occurrence of a bridging effect between the polysilicon gate and the source/drain regions caused by the forming of undesired silicide over the spacer structure due to lateral diffusion of the silicide from the polysilicon gate. Moreover, this method is characterized in the use of two different materials to respectively form the sacrificial layer and the field oxide layers, thus allowing the field oxide layers to remain substantially intact during the removal of the sacrificial layer through etching. This feature can help prevent the occurrence of leakage current from the metal plug to the substrate.
Inventors
- 👤 Der-Yuan Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:47
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0212; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
164 words
A method for forming self-aligned silicide in an integrated circuit without causing a bridging effect, the method comprising the steps of: preparing a semiconductor substrate; forming a gate oxide layer at a selected location over the substrate; forming a polysilicon gate over the gate oxide layer; forming an etch-end layer over the polysilicon gate; forming a sacrificial layer over the etch-end layer; forming a spacer structure on the sidewall of the stacked structure of the gate oxide layer, the polysilicon gate, the etch-end layer, and the sacrificial layer; forming source/drain regions in the substrate; performing an etching process to remove the entire sacrificial layer so that the etch-end layer is exposed; removing the entire etch-end layer; forming a metallization layer over the entire wafer; performing a thermal annealing process to allow those portions of the metallization layer that are laid directly over the polysilicon gate and the source/drain regions to be converted into silicide; and removing all the unreacted part of the metallization layer.
Claim 2
Independent Claim
164 words
A method for forming self-aligned silicide in an integrated circuit without causing a bridging effect, the method comprising the steps of: preparing a semiconductor substrate; forming a gate oxide layer at a selected location over the substrate; forming a polysilicon gate over the gate oxide layer; forming an etch-end layer over the polysilicon gate; forming a sacrificial layer over the etch-end layer; forming a spacer structure on the sidewall of the stacked structure of the gate oxide layer, the polysilicon gate, the etch-end layer, and the sacrificial layer; forming source/drain regions in the substrate; performing an etching process to remove the entire sacrificial layer so that the etch-end layer is exposed; removing the entire etch-end layer; forming a metallization layer over the entire wafer; performing a thermal annealing process to allow those portions of the metallization layer that are laid directly over the polysilicon gate and the source/drain regions to be converted into silicide; and removing all the unreacted part of the metallization layer.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein the sacrificial layer is formed from polysilicon.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein the etch-end layer is formed from silicon oxide.
Claim 5
Dependent Claim
14 words
The method of claim 2, wherein the etch-end layer is formed from silicon oxide.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein the etch-end layer is formed to a thickness of 20-80 Å.
Claim 7
Dependent Claim
17 words
The method of claim 4, wherein the etch-end layer is formed to a thickness of 20-80 Å.
Claim 8
Dependent Claim
119 words
The method of claim 1, wherein the step of forming the source/drain regions comprises the substeps of: performing a first ion-implantation process prior to the step of forming the spacer structure, so as to form lightly-doped areas in the substrate on both sides of the stacked structure of the gate oxide layer, the polysilicon gate, the etch-end layer, and the sacrificial layer; and performing a second ion-implantation process after the etch-end layer is removed and prior to the forming of the metallization layer, so as to form heavily-doped areas in the substrate and meanwhile allow the polysilicon gate to be doped to increase the conductivity thereof, the lightly-doped areas and the heavily-doped areas in combination constituting the source/drain regions.
Claim 9
Dependent Claim
15 words
The method of claim 1, wherein the metallization layer is formed from a refractory metal.
Claim 10
Dependent Claim
11 words
The method of claim 8, wherein the refractory metal is titanium.
Claim 11
Dependent Claim
14 words
The method of claim 1, wherein the thermal annealing process is an RTA process.
Claim 12
Independent Claim
171 words
A method for forming self-aligned silicide in an integrated circuit without causing a bridging effect, the method comprising the steps of: preparing a semiconductor substrate; forming a gate oxide layer at a selected location over the substrate; forming a polysilicon gate over the gate oxide layer; forming an etch-end layer from oxide over the polysilicon gate; forming a sacrificial layer from polysilicon over the etch-end layer; forming a spacer structure on the sidewall of the stacked structure of the gate oxide layer, the polysilicon gate, the oxide etch-end layer, and the polysilicon sacrificial layer; forming source/drain regions in the substrate; performing an etching process to remove the polysilicon sacrificial layer so that the oxide etch-end layer is exposed; removing the oxide etch-end layer; forming a metallization layer over the entire wafer; performing a thermal annealing process to allow those portions of the metallization layer that are laid directly over the polysilicon gate and the source/drain regions to be converted into silicide; and removing all the unreacted part of the metallization layer.
Claim 13
Independent Claim
171 words
A method for forming self-aligned silicide in an integrated circuit without causing a bridging effect, the method comprising the steps of: preparing a semiconductor substrate; forming a gate oxide layer at a selected location over the substrate; forming a polysilicon gate over the gate oxide layer; forming an etch-end layer from oxide over the polysilicon gate; forming a sacrificial layer from polysilicon over the etch-end layer; forming a spacer structure on the sidewall of the stacked structure of the gate oxide layer, the polysilicon gate, the oxide etch-end layer, and the polysilicon sacrificial layer; forming source/drain regions in the substrate; performing an etching process to remove the polysilicon sacrificial layer so that the oxide etch-end layer is exposed; removing the oxide etch-end layer; forming a metallization layer over the entire wafer; performing a thermal annealing process to allow those portions of the metallization layer that are laid directly over the polysilicon gate and the source/drain regions to be converted into silicide; and removing all the unreacted part of the metallization layer.
Claim 14
Dependent Claim
122 words
The method of claim 11, wherein the step of forming the source/drain regions comprises the substeps of: performing a first ion-implantation process prior to the step of forming the spacer structure, so as to form lightly-doped areas in the substrate on both sides of the stacked structure of the gate oxide layer, the polysilicon gate, the oxide etch-end layer, and the polysilicon sacrificial layer; and performing a second ion-implantation process after the oxide etch-end layer is removed and prior to the forming of the metallization layer, so as to form heavily-doped areas in the substrate and meanwhile allow the polysilicon gate to be doped to increase the conductivity thereof, the lightly-doped areas and the heavily-doped areas in combination constituting the source/drain regions.
Claim 15
Dependent Claim
18 words
The method of claim 11, wherein the oxide etch-end layer is formed to a thickness of 20-80 Å.
Claim 16
Dependent Claim
18 words
The method of claim 12, wherein the oxide etch-end layer is formed to a thickness of 20-80 Å.
Claim 17
Dependent Claim
15 words
The method of claim 11, wherein the metallization layer is formed from a refractory metal.
Claim 18
Dependent Claim
15 words
The method of claim 12, wherein the metallization layer is formed from a refractory metal.
Claim 19
Dependent Claim
11 words
The method of claim 15, wherein the refractory metal is titanium.
Claim 20
Dependent Claim
11 words
The method of claim 16, wherein the refractory metal is titanium.
Claim 21
Dependent Claim
14 words
The method of claim 11, wherein the thermal annealing process is an RTA process.
Claim 22
Dependent Claim
18 words
The method of claim 17, wherein the thermal annealing process is performed at a temperature of 800-850° C.
References Cited (Backward Citations)
US5879997A
Cited
US5891784A
Cited
US5496750A
Cited
US5656519A
Cited
US5686331A
Cited
US5872039A
Cited
US5902125A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-01 | 2004-01-31 | 2004-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-01 | 2008-01-31 | 2008-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-01 | 2012-01-31 | 2012-08-01 | $7700.00 | Window Closed / Lapsed |