Patent US3591176A successfully refreshed from Google Patents.
US5891784A
Expired / Lapsed
US
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Transistor fabrication method
Assignee: Bell Semiconductor LLC
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Filing: 1995-04-27
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Granted: 1999-04-06
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Expires: 2015-04-27
Abstract
Abstract A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.
Inventors
- 👤 Wan Yee Cheung
- 👤 Sailesh Chittipeddi
- 👤 Chong-Cheng Fu
- 👤 Taeho Kook
- 👤 Avinoam Kornblit
- 👤 Steven Alan Lytle
- 👤 Kurt George Steiner
- 👤 Tungsheng Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:32
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10P76/2043; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D64/00; H10D64/01; H10D64/017; H10D30/0227; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/952
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
156 words
A method of semiconductor integrated circuit fabrication comprising: forming a dielectric layer upon a substrate; forming a conductive layer upon said dielectric layer; forming a material layer overlying said conductive layer; forming an anti-reflective coating upon said material layer; forming a patterned resist upon said antireflective coating by exposing said resist to light; said anti-reflective coating having a thickness chosen in conjunction with a thickness of said material layer so as to reduce the total reflectivity of said light from said anti-reflective coating, said material and conductive layers; etching said anti-reflective coating; at least partially etching said material layer to thereby form a raised feature; removing said resist; and then using said raised feature as a mask, anistropically etching said conductive layer and said dielectric layer, thereby forming a gate; forming source and drain regions; and then removing said mask; wherein the material layer is a silicon oxide layer whose doping increases from bottom to top.
Claim 2
Independent Claim
156 words
A method of semiconductor integrated circuit fabrication comprising: forming a dielectric layer upon a substrate; forming a conductive layer upon said dielectric layer; forming a material layer overlying said conductive layer; forming an anti-reflective coating upon said material layer; forming a patterned resist upon said antireflective coating by exposing said resist to light; said anti-reflective coating having a thickness chosen in conjunction with a thickness of said material layer so as to reduce the total reflectivity of said light from said anti-reflective coating, said material and conductive layers; etching said anti-reflective coating; at least partially etching said material layer to thereby form a raised feature; removing said resist; and then using said raised feature as a mask, anistropically etching said conductive layer and said dielectric layer, thereby forming a gate; forming source and drain regions; and then removing said mask; wherein the material layer is a silicon oxide layer whose doping increases from bottom to top.
Claim 3
Dependent Claim
20 words
The method of claim 1 in which said material layer is formed from the group consisting of BPSG and PSG.
Claim 4
Dependent Claim
50 words
The method of claim 1 further including the steps of: prior to removal of said material layer, blanket depositing a refractory metal upon said material layer and upon said source and drain; heating said refractory metal to form a silicide upon said source and drain and not upon said gate.
Claim 5
Dependent Claim
61 words
The method of claim 1 further including the steps of: forming a protective layer over said source and drain; exposing said conductive layer of said gate by removing said material layer; depositing a refractory metal upon said conductive layer and upon said protective layer; heating said refractory metal to form silicide upon said gate and not upon said source and drain.
Claim 6
Dependent Claim
49 words
The method of claim 1 further including the steps, prior to removal of said material layer, of: blanket depositing a refractory metal upon said gate and source and drain region; reacting said refractory metal to form a silicide upon said source and drain region and not upon said gate.
Claim 7
Dependent Claim
24 words
The method of claim 1, further including the steps of: blanket depositing a refractory metal upon said gate and said source and drain region.
References Cited (Backward Citations)
US5185279A
Cited
US5354387A
Cited
US5139974A
Cited
US5302538A
Cited
US5445987A
Cited
US5747388A
Cited
US5352631A
Cited
US5395780A
Cited
US5346867A
Cited
US5441914A
Cited
US5482894A
Cited
US5604157A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |