Method of manufacturing a nonvolatile memory including a memory cell having a MISFET

Claim 1

A method of manufacturing a nonvolatile memory including a memory cell having a single MISFET, comprising the steps of: forming a first gate insulating film over a principal surface of a semiconductor substrate; forming a first conductor layer over said first gate insulating film; forming a second gate insulating film over said first conductor layer; forming a damage preventing film over said second gate insulating film; patterning said damage preventing film, said second gate insulating film and said first conductor layer in a stripe shape to extend in a first direction; forming semiconductor regions, in self-alignment with said first conductor layer in a stripe shape, extending in said first direction, in said semiconductor substrate, at both sides of the damage preventing film, second gate insulating film and first conductor layer patterned in the stripe shape, by ion implantation of ions of a first impurity, by using said stripe-shaped damage preventing film as a mask, wherein said damage preventing film acts to prevent said second gate insulating film from being implanted with said first impurity; after forming the semiconductor regions, removing said damage preventing film, without removing said second gate insulating film; forming a second conductor layer over said second gate insulating film and over said principal surface after said damage preventing film has been removed; and forming the control gate electrode and floating gate electrode of said MISFET by etching said second conductor layer, said second gate insulating film and said first conductor layer selectively, wherein one of said semiconductor regions acts as a first data line and is formed integrally with the source or drain region of said MISFET.

Claim 2

A method of manufacturing a nonvolatile memory including a memory cell having a single MISFET, comprising the steps of: forming a first gate insulating film over a principal surface of a semiconductor substrate; forming a first conductor layer over said first gate insulating film; forming a second gate insulating film over said first conductor layer; forming a damage preventing film over said second gate insulating film; patterning said damage preventing film, said second gate insulating film and said first conductor layer in a stripe shape to extend in a first direction; forming semiconductor regions, in self-alignment with said first conductor layer in a stripe shape, extending in said first direction, in said semiconductor substrate, at both sides of the damage preventing film, second gate insulating film and first conductor layer patterned in the stripe shape, by ion implantation of ions of a first impurity, by using said stripe-shaped damage preventing film as a mask, wherein said damage preventing film acts to prevent said second gate insulating film from being implanted with said first impurity; after forming the semiconductor regions, removing said damage preventing film, without removing said second gate insulating film; forming a second conductor layer over said second gate insulating film and over said principal surface after said damage preventing film has been removed; and forming the control gate electrode and floating gate electrode of said MISFET by etching said second conductor layer, said second gate insulating film and said first conductor layer selectively, wherein one of said semiconductor regions acts as a first data line and is formed integrally with the source or drain region of said MISFET.

Claim 10

A method of manufacturing a semiconductor memory device including memory cells, comprising the steps of: forming a first gate insulating film over a main surface of a semiconductor substrate; forming a first conductive film over said first gate insulating film; forming a second gate insulating film over said first conductive film; forming a damage preventing film over said second gate insulating film; patterning said damage preventing film, said second gate insulating film and said first conductive film in a stripe shape in such a manner that said damage preventing film, said second gate insulating film and said first conductive film are left on first regions of said main surface and in such a manner that said damage preventing film, said second gate insulating film and said first conductive film are removed from second regions of said main surface, wherein said first and second regions extend in a first direction, side by side in such a manner that a first region is formed between adjacent second regions and in such a manner that a second region is formed between adjacent first regions; introducing an impurity within each of said second regions in self-alignment with said damage preventing film with said stripe shape to form first semiconductor regions in said semiconductor substrate below said second regions, wherein said first semiconductor regions extend below said second regions adjacent to each other in said second direction and are formed in self-alignment with said first conductive film in a stride shape, and wherein said damage preventing film acts to prevent said second gate insulating film from being introduced with said impurity; removing said damage preventing film with said stripe shape, after introducing the impurity; forming a first insulating film over both side surfaces of said first conductive films with said stripe shape and over said second regions; forming a second conductive film over said first insulating film and over said second gate insulating film with said stripe shape; and patterning said second conductive film and said first conductive film with said stripe shape to form word lines and floating gate electrodes, respectively, wherein said word lines extend in said second direction and are spaced apart from each other in said first direction, wherein said floating gate electrodes are formed below said word lines and are spaced apart from each other in said first direction, wherein each of the memory cells is comprised of a single MISFET including said first gate insulating film, said floating gate electrode, said second gate insulating film, a control gate electrode and said first semiconductor regions serving as source and drain regions of said MISFET, wherein said memory cells are arranged in said first and second directions in such a manner that said first semiconductor regions are common for memory cells adjacent to each other in said second direction and in such a manner that said first semiconductor regions are common for said memory cells arranged in said first direction.

Claim 11

A method of manufacturing a semiconductor memory device including memory cells, comprising the steps of: forming a first gate insulating film over a main surface of a semiconductor substrate; forming a first conductive film over said first gate insulating film; forming a second gate insulating film over said first conductive film; forming a damage preventing film over said second gate insulating film; patterning said damage preventing film, said second gate insulating film and said first conductive film in a stripe shape in such a manner that said damage preventing film, said second gate insulating film and said first conductive film are left on first regions of said main surface and in such a manner that said damage preventing film, said second gate insulating film and said first conductive film are removed from second regions of said main surface, wherein said first and second regions extend in a first direction, side by side in such a manner that a first region is formed between adjacent second regions and in such a manner that a second region is formed between adjacent first regions; introducing an impurity within each of said second regions in self-alignment with said damage preventing film with said stripe shape to form first semiconductor regions in said semiconductor substrate below said second regions, wherein said first semiconductor regions extend below said second regions adjacent to each other in said second direction and are formed in self-alignment with said first conductive film in a stride shape, and wherein said damage preventing film acts to prevent said second gate insulating film from being introduced with said impurity; removing said damage preventing film with said stripe shape, after introducing the impurity; forming a first insulating film over both side surfaces of said first conductive films with said stripe shape and over said second regions; forming a second conductive film over said first insulating film and over said second gate insulating film with said stripe shape; and patterning said second conductive film and said first conductive film with said stripe shape to form word lines and floating gate electrodes, respectively, wherein said word lines extend in said second direction and are spaced apart from each other in said first direction, wherein said floating gate electrodes are formed below said word lines and are spaced apart from each other in said first direction, wherein each of the memory cells is comprised of a single MISFET including said first gate insulating film, said floating gate electrode, said second gate insulating film, a control gate electrode and said first semiconductor regions serving as source and drain regions of said MISFET, wherein said memory cells are arranged in said first and second directions in such a manner that said first semiconductor regions are common for memory cells adjacent to each other in said second direction and in such a manner that said first semiconductor regions are common for said memory cells arranged in said first direction.