Method and apparatus for controlling the data rate of a clocking circuit

Claim 2

A data rate control circuit, comprising: a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

Claim 3

The data rate control circuit of claim 1 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

Claim 4

The data rate control circuit of claim 1 wherein the clocking circuit comprises a shift register.

Claim 5

The data rate control circuit of claim 1 wherein the clocking circuit comprises a counter latch.

Claim 6

The data rate control circuit of claim 1 wherein the one logic level comprises a logic one logic level.

Claim 7

The data rate control circuit of claim 1 wherein the clocking circuit comprises a circuit that clocks on transitions of the first clock signal to a logic one logic level in response to receiving the steady state voltage on the output line.

Claim 8

The data rate control circuit of claim 1 wherein the clocking circuit comprises a circuit that clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the output line.

Claim 9

The data rate control circuit of claim 1 wherein the steady state voltage comprises a positive voltage.

Claim 10

The data rate control circuit of claim 1 wherein the steady state voltage comprises zero volts.

Claim 11

The data rate control circuit of claim 1 wherein the switching circuit comprises a switching element.

Claim 12

The data rate control circuit of claim 1 wherein the switching circuit comprises an antifuse.

Claim 13

The data rate control circuit of claim 1 wherein the switching circuit comprises a transistor.

Claim 14

A data rate control circuit, comprising a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency, a second phase, and a first duty cycle; a duty cycle changing circuit coupled to the second clock line and having an output line, the duty cycle changing circuit receiving the second clock signal and a reference signal, the reference signal having a second duty cycle, the duty cycle changing circuit operative in a first mode to couple the second clock line to the output line, and operative in a second mode to couple the reference signal to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving a signal on the output line having the first duty cycle and structured to clock on only one edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

Claim 15

A data rate control circuit, comprising a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency, a second phase, and a first duty cycle; a duty cycle changing circuit coupled to the second clock line and having an output line, the duty cycle changing circuit receiving the second clock signal and a reference signal, the reference signal having a second duty cycle, the duty cycle changing circuit operative in a first mode to couple the second clock line to the output line, and operative in a second mode to couple the reference signal to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving a signal on the output line having the first duty cycle and structured to clock on only one edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

Claim 16

The date rate control circuit of claim 13 wherein the first duty cycle is 50% and the second duty cycle is 100%.

Claim 17

The date rate control circuit of claim 13 wherein the first duty cycle is 50% and the second duty cycle is 0%.

Claim 18

The data rate control circuit of claim 13 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

Claim 19

The data rate control circuit of claim 13 wherein the clocking circuit comprises a shift register.

Claim 20

The data rate control circuit of claim 13 wherein the clocking circuit comprises a counter latch.

Claim 21

The data rate control circuit of claim 13 wherein the first edge is a rising edge and the second edge is a falling edge.

Claim 22

The data rate control circuit of claim 13 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the rising edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

Claim 23

The data rate control circuit of claim 13 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the falling edge of the first clock signal in response to receiving a signal on the output line having the second duty cycle.

Claim 24

The data rate control circuit of claim 13 wherein the duty cycle changing circuit comprises a switching element.

Claim 25

The data rate control circuit of claim 13 wherein the duty cycle changing circuit comprises an antifuse.

Claim 26

The data rate control circuit of claim 13 wherein the duty cycle changing circuit comprises a transistor.

Claim 27

A data rate control circuit, comprising a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency, and a second phase; a frequency changing circuit coupled to the second clock line and having an output line, the switching circuit receiving the second clock signal and a reference signal, the reference signal having a second frequency, the switching circuit operative in a first mode to couple the second clock line to the output line, and operable in a second mode to couple the reference signal to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving a signal on the output line having the first frequency, and clocking on only one edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

Claim 28

A data rate control circuit, comprising a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency, and a second phase; a frequency changing circuit coupled to the second clock line and having an output line, the switching circuit receiving the second clock signal and a reference signal, the reference signal having a second frequency, the switching circuit operative in a first mode to couple the second clock line to the output line, and operable in a second mode to couple the reference signal to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving a signal on the output line having the first frequency, and clocking on only one edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

Claim 29

The date rate control circuit of claim 25 wherein the first frequency is a positive number.

Claim 30

The date rate control circuit of claim 25 wherein the second frequency is zero.

Claim 31

The data rate control circuit of claim 25 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

Claim 32

The data rate control circuit of claim 25 wherein the clocking circuit comprises a shift register.

Claim 33

The data rate control circuit of claim 25 wherein the clocking circuit comprises a counter latch.

Claim 34

The data rate control circuit of claim 25 wherein the first edge is a rising edge and the second edge is a falling edge.

Claim 35

The data rate control circuit of claim 25 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the rising edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

Claim 36

The data rate control circuit of claim 25 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the falling edge of the first clock signal in response to receiving a signal on the output line having the second frequency.

Claim 37

The data rate control circuit of claim 25 wherein the frequency changing circuit comprises a switching element.

Claim 38

The data rate control circuit of claim 25 wherein the frequency changing circuit comprises an antifuse.

Claim 39

The data rate control circuit of claim 25 wherein the frequency changing circuit comprises a transistor.

Claim 40

A data rate control circuit, comprising: a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a fuse having a first end and a second end, the first end coupled to the second clock signal line; an antifuse having a first side and a second side, the first side coupled to a steady state voltage source and the second side coupled to the second end of the fuse; and a clocking circuit coupled to the first clock line and to the second side of the antifuse, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving the second clock signal through the fuse, and clocking on only one edge of the first clock signal in response to receiving the steady state voltage through the antifuse.

Claim 41

A data rate control circuit, comprising: a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a fuse having a first end and a second end, the first end coupled to the second clock signal line; an antifuse having a first side and a second side, the first side coupled to a steady state voltage source and the second side coupled to the second end of the fuse; and a clocking circuit coupled to the first clock line and to the second side of the antifuse, the clocking circuit structured to clock on both edges of the first clock signal in response to receiving the second clock signal through the fuse, and clocking on only one edge of the first clock signal in response to receiving the steady state voltage through the antifuse.

Claim 42

The data rate control circuit of claim 37 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

Claim 43

The data rate control circuit of claim 37 wherein the clocking circuit comprises a shift register.

Claim 44

The data rate control circuit of claim 37 wherein the clocking circuit comprises a counter latch.

Claim 45

The data rate control circuit of claim 37 wherein the first edge is a rising edge and the second edge is a falling edge.

Claim 46

The data rate control circuit of claim 37 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the rising edge of the first clock signal in response to receiving the steady state voltage on the output line.

Claim 47

The data rate control circuit of claim 37 wherein the first edge is a rising edge and the second edge is a falling edge, and the clocking circuit comprises a circuit that clocks on only the falling edge of the first clock signal in response to receiving the steady state voltage on the output line.

Claim 48

A data rate control circuit, comprising: a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency, a second phase, a third edge, and a fourth edge; a switching circuit coupled to the first clock line and the second clock line, the switching circuit having a first output line and a second output line, the switching circuit receiving the first clock signal on the first clock line, and the second clock signal on the second clock line, the switching circuit operative in a first mode to couple the first clock line to the first output line and to couple the second clock line to the second output line, and operative in a second mode to couple the first output line to a steady state voltage and to couple the second output line to a third clock signal, the third clock signal having the first frequency, a third phase, a fifth edge and a sixth edge; a clocking circuit coupled to the first output line and the second output line, the clocking circuit structured to clock when a signal on the first output line is a relatively high voltage and also structured to clock when a signal on the second output line is a relatively low voltage.

Claim 49

A data rate control circuit, comprising: a first clock line receiving a first clock signal, the first clock signal having a first frequency, a first phase, a first edge, and a second edge; a second clock line receiving a second clock signal, the second clock signal having the first frequency, a second phase, a third edge, and a fourth edge; a switching circuit coupled to the first clock line and the second clock line, the switching circuit having a first output line and a second output line, the switching circuit receiving the first clock signal on the first clock line, and the second clock signal on the second clock line, the switching circuit operative in a first mode to couple the first clock line to the first output line and to couple the second clock line to the second output line, and operative in a second mode to couple the first output line to a steady state voltage and to couple the second output line to a third clock signal, the third clock signal having the first frequency, a third phase, a fifth edge and a sixth edge; a clocking circuit coupled to the first output line and the second output line, the clocking circuit structured to clock when a signal on the first output line is a relatively high voltage and also structured to clock when a signal on the second output line is a relatively low voltage.

Claim 50

A memory device having an address bus, comprising: a memory array circuit comprising a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells; and an addressing circuit coupled to the address bus and the memory array circuit, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array responsive to a command word, the addressing circuit having a data rate control circuit, the data rate control circuit comprising: a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

Claim 51

A memory device having an address bus, comprising: a memory array circuit comprising a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells; and an addressing circuit coupled to the address bus and the memory array circuit, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array responsive to a command word, the addressing circuit having a data rate control circuit, the data rate control circuit comprising: a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

Claim 52

The memory device of claim 45 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

Claim 53

The memory device of claim 45 wherein the clocking circuit comprises a shift register.

Claim 54

The memory device of claim 45 wherein the clocking circuit comprises a counter latch.

Claim 55

The memory device of claim 45 wherein the one logic level comprises a logic one logic level.

Claim 56

The memory device of claim 45 wherein the clocking circuit comprises a circuit that clocks on transitions of the first clock signal to a logic one logic level in response to receiving the steady state voltage on the output line.

Claim 57

The memory device of claim 45 wherein the clocking circuit comprises a circuit that clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the output line.

Claim 58

The memory device of claim 45 wherein the steady state voltage comprises a positive voltage.

Claim 59

The memory device of claim 45 wherein the steady state voltage comprises zero volts.

Claim 60

The memory device of claim 45 wherein the switching circuit comprises a switching element.

Claim 61

The memory device of claim 45 wherein the switching circuit comprises an antifuse.

Claim 62

The memory device of claim 45 wherein the switching circuit comprises a transistor.

Claim 63

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, the memory device comprising: a memory array circuit comprising a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells; and an addressing circuit coupled to an address bus and the memory array circuit, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array responsive to a command word, the addressing circuit having a data rate control circuit, the data rate control circuit comprising: a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

Claim 64

A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, the memory device comprising: a memory array circuit comprising a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digit for each column of memory cells; and an addressing circuit coupled to an address bus and the memory array circuit, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array responsive to a command word, the addressing circuit having a data rate control circuit, the data rate control circuit comprising: a first clock line receiving a first clock signal that transitions between a pair of logic levels, the first clock signal having a first frequency and a first phase; a second clock line receiving a second clock signal, the second clock signal having the first frequency and a second phase; a switching circuit coupled to the second clock line to receive the second clock signal, the switching circuit operative in a first mode to couple the second clock line to an output line, and operative in a second mode to couple a steady state voltage to the output line; and a clocking circuit coupled to the first clock line and the output line, the clocking circuit structured to clock on transitions of the first clock signal to both logic levels in response to receiving the second clock signal on the output line, and clocking on transitions of the first clock signal to only one logic level in response to receiving the steady state voltage on the output line.

Claim 65

The computer system of claim 57 wherein the clocking circuit comprises a circuit that performs a predetermined function each time the clocking circuit clocks.

Claim 66

The computer system of claim 57 wherein the clocking circuit comprises a shift register.

Claim 67

The computer system of claim 57 wherein the clocking circuit comprises a counter latch.

Claim 68

The computer system of claim 57 wherein the one logic level comprises a logic one logic level.

Claim 69

The computer system of claim 57 wherein the clocking circuit comprises a circuit that clocks on transitions of the first clock signal to a logic one logic level in response to receiving the steady state voltage on the output line.

Claim 70

The computer system of claim 57 wherein the clocking circuit comprises a circuit that clocks on only transitions of the first clock signal to a logic zero logic level in response to receiving the steady state voltage on the output line.

Claim 71

The computer system of claim 57 wherein the steady state voltage comprises a positive voltage.

Claim 72

The computer system of claim 57 wherein the steady state voltage comprises zero volts.

Claim 73

The computer system of claim 57 wherein the switching circuit comprises a switching element.

Claim 74

The computer system of claim 57 wherein the switching circuit comprises an antifuse.

Claim 75

The computer system of claim 57 wherein the switching circuit comprises a transistor.