US5564042A — Asynchronous clock switching between first and se…

Claim 1

Independent Claim 396 words

A semiconductor chip having a microprocessor thereon that is operable in at least one mode in conjunction with at least one bus for exchange of data between said microprocessor circuit and circuitry external thereto, and being clocked by a clock signal generated on said semiconductor chip that switches between a first and a second state, said bus being operable at a first clock rate, comprising: a) processing circuitry for processing digital data, operable at said second clock rate or at said first clock rate, said second clock rate being faster than said first clock rate; b) first clock means for providing a first clock signal at said first clock rate; c) second clock means for providing a second clock signal, asynchronous to said first clock signal at said second clock rate; and d) clock switch means coupled to said first and said second clock means for sensing when said bus is to be used and for applying said first clock signal to said processing circuitry otherwise, said clock switch means including: c1) means, responsive to only the first and second clock rates, for determining a time at which to change the clock signal applied to said processing circuitry from said first clock signal to said second clock signal, c2) means for sensing, at said determined time, the first clock signal then being applied to said processing circuitry, and for applying the second clock signal to said processing circuitry at the next transition of said second clock signal to the alternate state of that sensed at said determined time, but only after said first clock signal has made a transition, after said determined time, from the sensed state to said alternate state; c3) means, responsive to only the first and second clock rates, for determining a time at which to change the clock signal applied to said processing circuitry from said second clock signal to said first clock signal, and c4) means for sensing, at said determined time, the second clock signal then being applied to said processing circuitry, and for applying the first clock signal to said processing circuitry at a transition just after the next transition of said first clock signal to the alternate state of that sensed at said determined time, but only after said second clock signal has made a transition, after said determined time, from the sensed state to said alternate state.

Claim 2

Dependent Claim 396 words

A semiconductor chip having a microprocessor thereon that is operable in at least one mode in conjunction with at least one bus for exchange of data between said microprocessor circuit and circuitry external thereto, and being clocked by a clock signal generated on said semiconductor chip that switches between a first and a second state, said bus being operable at a first clock rate, comprising: a) processing circuitry for processing digital data, operable at said second clock rate or at said first clock rate, said second clock rate being faster than said first clock rate; b) first clock means for providing a first clock signal at said first clock rate; c) second clock means for providing a second clock signal, asynchronous to said first clock signal at said second clock rate; and d) clock switch means coupled to said first and said second clock means for sensing when said bus is to be used and for applying said first clock signal to said processing circuitry otherwise, said clock switch means including: c1) means, responsive to only the first and second clock rates, for determining a time at which to change the clock signal applied to said processing circuitry from said first clock signal to said second clock signal, c2) means for sensing, at said determined time, the first clock signal then being applied to said processing circuitry, and for applying the second clock signal to said processing circuitry at the next transition of said second clock signal to the alternate state of that sensed at said determined time, but only after said first clock signal has made a transition, after said determined time, from the sensed state to said alternate state; c3) means, responsive to only the first and second clock rates, for determining a time at which to change the clock signal applied to said processing circuitry from said second clock signal to said first clock signal, and c4) means for sensing, at said determined time, the second clock signal then being applied to said processing circuitry, and for applying the first clock signal to said processing circuitry at a transition just after the next transition of said first clock signal to the alternate state of that sensed at said determined time, but only after said second clock signal has made a transition, after said determined time, from the sensed state to said alternate state.

Claim 3

Dependent Claim 110 words

A circuit according to claim 1, wherein said processor is clocked by at least two clock signals having the same frequency but different phase with respect to one another by a predetermined phase difference, wherein: a) said first clock means and said second clock means provide said first clock signal and said second clock signal, respectively, each as two applied clock signals differing in phase by said predetermined phase difference; and b) said clock switch means comprises means for simultaneously controlling the transition between said first clock signal and said second clock signal for each of the applied clock signals related respectively to said first and said second clock signals.

Claim 4

Dependent Claim 117 words

An integrated circuit chip, comprising: a) a fast and slow clock, where the fast clock is faster than and asynchronous to the slow clock; b) a functional circuit block, deigned to be clocked by said fast clock when performing internal processing, and designed to be clocked by said slow clock when doing external processing of signals going to and from the function circuit block; and c) means for switching the functional circuit block from the slow clock to the fast clock at a very next available transition of the fast clock: and from the fast clock to the slow clock in at most two transitions of the slow clock: each without a third clock coordinating the switching.

Claim 5

Dependent Claim 117 words

An integrated circuit chip, comprising: a) a fast and slow clock, where the fast clock is faster than and asynchronous to the slow clock; b) a functional circuit block, deigned to be clocked by said fast clock when performing internal processing, and designed to be clocked by said slow clock when doing external processing of signals going to and from the function circuit block; and c) means for switching the functional circuit block from the slow clock to the fast clock at a very next available transition of the fast clock: and from the fast clock to the slow clock in at most two transitions of the slow clock: each without a third clock coordinating the switching.

Claim 6

Dependent Claim 18 words

The integrated circuit chip of claim 3, wherein the functional circuit block is a portion of a microprocessor.

Claim 7

Dependent Claim 15 words

The integrated circuit chip of claim 3, wherein the functional circuit block is a microprocessor.

Claim 8

Dependent Claim 160 words

An integrated circuit chip, comprising: a) a fast and slow clock, where the fast clock is faster than and asynchronous to the slow clock; b) a functional circuit block designed to be clocked by said fast clock when performing internal processing, and designed to be clocked by said slow clock when interfacing with signals from outside the functional circuit block thus performing external processing; and c) means for switching the functional circuit block operation from the slow clock to the fast clock at a very next transition of the fast clock, and from the fast clock to the slow clock in at most two transitions of the slow clock, wherein the switching is activated by a switching request received by the switching means and the switching is completed only in response to the fast and the slow clocks, wherein said switching means providing for faster asynchronous clock switching between the internal and the external processing and for being self timed.

Claim 9

Dependent Claim 160 words

An integrated circuit chip, comprising: a) a fast and slow clock, where the fast clock is faster than and asynchronous to the slow clock; b) a functional circuit block designed to be clocked by said fast clock when performing internal processing, and designed to be clocked by said slow clock when interfacing with signals from outside the functional circuit block thus performing external processing; and c) means for switching the functional circuit block operation from the slow clock to the fast clock at a very next transition of the fast clock, and from the fast clock to the slow clock in at most two transitions of the slow clock, wherein the switching is activated by a switching request received by the switching means and the switching is completed only in response to the fast and the slow clocks, wherein said switching means providing for faster asynchronous clock switching between the internal and the external processing and for being self timed.

Claim 10

Dependent Claim 33 words

The integrated circuit chip of claim 6, wherein the switching means operates only in response to the fast and slow clock, and wherein the functional circuit block is a portion of a microprocessor.

Claim 11

Dependent Claim 30 words

The integrated circuit chip of claim 6, wherein the switching means operates only in response to the fast and slow clock, and wherein the functional circuit block is a microprocessor.

Claim 12

Dependent Claim 171 words

An integrated circuit chip comprising: a) a fast and slow clock, where the fast clock is faster than and asynchronous to the slow clock, and the fast clock is a fractional proportion difference from the slow clock; b) a functional circuit block designed to be clocked by said fast clock when performing internal processing, and designed to be clocked by said slow clock when exchanging signals from outside the functional circuit block thus performing external processing; and c) means for switching the functional circuit block operation from the slow clock to the fast clock within one fast clock cycle to enable internal processing, and from the fast clock to the slow clock within two slow clock cycles to enable external processing, wherein the switching means is initiated by receiving a switching request and is completed either by the end of the fast clock concluding a first full clock cycle to perform internal processing, or by the end of the slow clock concluding a first full clock cycle to perform external processing.

Claim 13

Dependent Claim 171 words

An integrated circuit chip comprising: a) a fast and slow clock, where the fast clock is faster than and asynchronous to the slow clock, and the fast clock is a fractional proportion difference from the slow clock; b) a functional circuit block designed to be clocked by said fast clock when performing internal processing, and designed to be clocked by said slow clock when exchanging signals from outside the functional circuit block thus performing external processing; and c) means for switching the functional circuit block operation from the slow clock to the fast clock within one fast clock cycle to enable internal processing, and from the fast clock to the slow clock within two slow clock cycles to enable external processing, wherein the switching means is initiated by receiving a switching request and is completed either by the end of the fast clock concluding a first full clock cycle to perform internal processing, or by the end of the slow clock concluding a first full clock cycle to perform external processing.

Claim 14

Dependent Claim 32 words

The integrated circuit chip of claim 9, wherein the switching means operates only in response to the fast and slow clock, and the functional circuit block is a portion of a microprocessor.

Claim 15

Dependent Claim 29 words

The integrated circuit chip of claim 9, wherein the switching means operates only in response to the fast and slow clock, and the functional circuit block is a microprocessor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-10-08	2000-04-08	2000-10-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-10-08	2004-04-08	2004-10-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-10-08	2008-04-08	2008-10-08	$7700.00	Window Closed / Lapsed

Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions

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