Abstract A single-chip microcomputer has a clock-signal generating circuit which includes a main system-clock oscillation circuit for generating a main clock-signal, a sub system-clock oscillation circuit for generating a sub clock-signal, a selector flag setter for setting a selector flag, an oscillation control flag setter for setting an oscillation control flag, and a synchronization control circuit for effecting synchronization between the main clock-signal and the sub clock-signal. The clock-signal generating circuit of the invention has a logic circuit which takes a logical AND operation of outputs of the oscillation control flag setter, the selector flag setter and the synchronization control circuit and which outputs an oscillation control signal for stopping oscillating operation of the main system-clock oscillation circuit. The main system-clock oscillation circuit automatically stops upon completion of the clock-signal switching operation, so that a CPU does not require a stand-by period for the switching of clock-signals and this results in the enhancement of processing capability of the CPU and results in the reduction of the power consumption.
A single-chip microcomputer provided with a clock-signal generating circuit comprising: a main system-clock oscillation circuit and a sub system-clock oscillation circuit; a selector for outputting a clock-signal by making a selection between a main clock-signal which is an output of said main system-clock oscillation circuit and a sub clock-signal which is an output of said sub system-clock oscillation circuit; a selector flag setter for setting a selector flag signal to designate the selection to be made by said selector; an oscillation control flag setter for setting an oscillation control flag signal to control the oscillating operation of said main system-clock oscillation circuit; a synchronization control circuit for making the synchronization between said main clock-signal and said sub clock-signal and outputting a synchronization signal; and a means for taking a logical AND operation of said oscillation control flag signal from said oscillation control flag setter, said selector flag signal from said selector flag setter and said synchronization signal from said synchronization control circuit and outputting an oscillation control signal for stopping the oscillating operation of said main system-clock oscillation circuit.
Claim 2
Dependent Claim
179 words
A single-chip microcomputer provided with a clock-signal generating circuit comprising: a main system-clock oscillation circuit and a sub system-clock oscillation circuit; a selector for outputting a clock-signal by making a selection between a main clock-signal which is an output of said main system-clock oscillation circuit and a sub clock-signal which is an output of said sub system-clock oscillation circuit; a selector flag setter for setting a selector flag signal to designate the selection to be made by said selector; an oscillation control flag setter for setting an oscillation control flag signal to control the oscillating operation of said main system-clock oscillation circuit; a synchronization control circuit for making the synchronization between said main clock-signal and said sub clock-signal and outputting a synchronization signal; and a means for taking a logical AND operation of said oscillation control flag signal from said oscillation control flag setter, said selector flag signal from said selector flag setter and said synchronization signal from said synchronization control circuit and outputting an oscillation control signal for stopping the oscillating operation of said main system-clock oscillation circuit.
Claim 3
Dependent Claim
87 words
A single-chip microcomputer according to claim 1, in which said means for producing the oscillation control signal comprises a logic circuit formed by an AND gate receiving said oscillation control flag signal, said selector flag signal and said synchronization signal; an inverter receiving said oscillation control flag signal; and an SR flip-flop having a set input receiving an output from said AND gate, a reset input receiving an output from said inverter and an output forwarding out said oscillation control signal to said main system-clock oscillation circuit.