Dual operating speed switchover arrangement for CPU

Claim 1

In a data processing system including a system bus and a CPU coupled thereto wherein the CPU is responsive to a clock signal provided from the system bus for establishing the operating speed of the CPU and the data processing system, an arrangement for selecting the operating speed of the data processing system comprising: user responsive switch means for generating a first control signal when said switch means is in a first position and a second control signal when said switch means is in a second position; logic means including first and second clock means coupled to the system bus and to said user responsive switch means and responsive to said first and second control signals for respectively providing a first clock signal from said first clock means to the CPU via the system bus upon receipt of said first control signal from said user responsive switch means whereupon the data processing system operates at a first speed or for providing a second clock signal from said second clock means to the CPU via the system bus upon receipt of said second control signal from said user responsive switch means whereupon the data processing system operates at a second speed, wherein said logic means is further coupled to the CPU and is responsive to status signals output therefrom for generating a third control signal; feedback means coupling said logic means to said switch means for providing said third control signal thereto for synchronizing said first and second control signals with said third control signal; and a system memory coupled to the system bus, wherein said third control signal is either a memory read signal or a memory write signal for synchronizing said first and second control signals and a change in data processing system operating speed associated therewith with a change in operation of said memory such that a change in data processing system operating speed occurs only after the completion of a memory read or write operation.