US5059925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for transparently switching clock sources
Assignee: Cisco Technology Inc
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Filing: 1990-09-28
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Granted: 1991-10-22
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Expires: 2010-09-28
Abstract
Abstract A method and apparatus for stably maintaining an output clock signal from a phase-locked loop (PLL) frequency multiplier when switching from one clock source to another clock source is described. This method and apparatus maintains the phase relationship between the external signal to the phase detector and the feedback signal from the divider to the phase detector.
Inventors
- 👤 John D. Weisbloom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:14
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/16; H03L7/18; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H04J3/0688
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
376 words
A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising: (a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state; (b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting; (c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state; (d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical AND of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.
Claim 2
Dependent Claim
376 words
A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising: (a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state; (b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting; (c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state; (d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical AND of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.
Claim 3
Dependent Claim
36 words
The circuit for maintaining a stable output from a phase-locked loop frequency multiplier of claim 1, wherein said first type of state is a high state and said second type of state is a low state.
Claim 4
Dependent Claim
376 words
A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising an exclusive-OR circuit, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising: (a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state; (b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting; (c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state; (d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical AND of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.
Claim 5
Dependent Claim
376 words
A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising an exclusive-OR circuit, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising: (a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state; (b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting; (c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state; (d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical AND of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.
Claim 6
Dependent Claim
36 words
The circuit for maintaining a stable output from a phase-locked loop frequency multiplier of claim 3, wherein said first type of state is a high state and said second type of state is a low state.
Claim 7
Dependent Claim
376 words
A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising: (a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state; (b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting; (c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state; (d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical OR of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.
Claim 8
Dependent Claim
376 words
A circuit for maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising: (a) a load circuit coupled to receive as a first input an output of said divider of said phase-locked loop frequency multiplier circuit, said load circuit changing its output load signal from a first type of state to a second type of state when said second input signal is selected and the output of said divider changes from said first type of state to said second type of state, said divider of said phase-locked loop frequency multiplier circuit coupled to receive said load signal, said divider cleared when said load signal is in said second type of state; (b) a first switch coupled to receive said first input signal and said second input signal, said first switch for switching its output from said first input signal to said second input signal when said second input signal is selected, said load circuit coupled to receive as a second input said first switch output signal, said load circuit changing said load signal from said second type of state to said first type of state when said second input signal is selected and said first switch output signal changes from said first type of state to said second type of state, said load signal in said first type of state causing said divider of said phase-locked loop frequency multiplier circuit to continue counting; (c) a second switch coupled to receive said first input signal, said second input signal, and said load signal, said second switch for switching its output from said first input signal to said second input signal when said second input signal is selected and said load signal changes from said second type of state to said first type of state; (d) a logic circuit coupled to receive said load signal and said second switch output signal, said logic circuit for generating the logical OR of said load signal and said second switch output signal, said logic circuit output coupled to the input of said phase-locked loop frequency multiplier circuit.
Claim 9
Dependent Claim
36 words
The circuit for maintaining a stable output from a phase-locked loop frequency multiplier of claim 5, wherein said first type of state is a low state and said second type of state is a high state.
Claim 10
Independent Claim
183 words
A method of maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising the steps of: (a) continuously clearing the divider of said phase-locked loop frequency multiplier circuit when said first input signal changes from a first type of state to a second type of state; (b) holding the input to said phase-locked loop frequency multiplier circuit in said second type of state; (c) no longer clearing the divider of said phase-locked loop frequency multiplier circuit when said second input signal changes from said second type of state to said first type of state; (d) switching the input to said phase-locked loop frequency multiplier circuit from said first input signal to said second input signal when said second input signal is in said second type of state and before the divider of said phase-locked loop frequency multiplier circuit has continued counting and outputted a change in type of state.
Claim 11
Independent Claim
183 words
A method of maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising a phase detector, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising the steps of: (a) continuously clearing the divider of said phase-locked loop frequency multiplier circuit when said first input signal changes from a first type of state to a second type of state; (b) holding the input to said phase-locked loop frequency multiplier circuit in said second type of state; (c) no longer clearing the divider of said phase-locked loop frequency multiplier circuit when said second input signal changes from said second type of state to said first type of state; (d) switching the input to said phase-locked loop frequency multiplier circuit from said first input signal to said second input signal when said second input signal is in said second type of state and before the divider of said phase-locked loop frequency multiplier circuit has continued counting and outputted a change in type of state.
Claim 12
Dependent Claim
36 words
The method of maintaining a stable output from a phase-locked loop frequency multiplier of claim 7 wherein said first type of state is a high state and said second type of state is a low state.
Claim 13
Dependent Claim
36 words
The method of maintaining a stable output from a phase-locked loop frequency multiplier of claim 7, wherein said first type of state is a low state and said second type of state is a high state.
Claim 14
Independent Claim
183 words
A method of maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising an exclusive-OR circuit, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising the steps of: (a) continuously clearing the divider of said phase-locked loop frequency multiplier circuit when said first input signal changes from a first type of state to a second type of state; (b) holding the input to said phase-locked loop frequency multiplier circuit in said second type of state; (c) no longer clearing the divider of said phase-locked loop frequency multiplier circuit when said second input signal changes from said second type of state to said first type of state; (d) switching the input to said phase-locked loop frequency multiplier circuit from said first input signal to said second input signal when said second input signal is in said second type of state and before the divider of said phase-locked loop frequency multiplier circuit has continued counting and outputted a change in type of state.
Claim 15
Independent Claim
183 words
A method of maintaining a stable output from a phase-locked loop frequency multiplier circuit, comprising an exclusive-OR circuit, a voltage controlled oscillator, and a divider, when switching an input to said phase-locked loop frequency multiplier circuit from a first input signal to a second input signal, comprising the steps of: (a) continuously clearing the divider of said phase-locked loop frequency multiplier circuit when said first input signal changes from a first type of state to a second type of state; (b) holding the input to said phase-locked loop frequency multiplier circuit in said second type of state; (c) no longer clearing the divider of said phase-locked loop frequency multiplier circuit when said second input signal changes from said second type of state to said first type of state; (d) switching the input to said phase-locked loop frequency multiplier circuit from said first input signal to said second input signal when said second input signal is in said second type of state and before the divider of said phase-locked loop frequency multiplier circuit has continued counting and outputted a change in type of state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-21 | 1995-04-22 | 1995-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-21 | 1999-04-22 | 1999-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-21 | 2003-04-22 | 2003-10-22 | $7700.00 | Window Closed / Lapsed |