Microprocessor embedded control system having an automatic clock slowdown circuit

Claim 1

An electrical system including an embedded microprocessor and peripherals, each one having a clock input pin, said microprocessor executing instructions at a speed dictated by a signal frequency received at said microprocessor clock input pin, a first portion of said system issuing a reset strobe in response to predetermined stimuli and a second portion of said system producing a first clock signal having a first frequency of substantially the maximum that said microprocessor can utilize, said microprocessor and said peripherals defining a pair of alternating clock phases by the timing of said reset strobe, said definition being possibly inconsistent when said first frequency is used, said system further including: a circuit which derives, from said first clock signal, a second clock signal having a slower frequency than said first clock signal and which temporarily switches said second clock signal into electrical connection to all said clock input pins during said reset strobe, said electrical connection continuing momentarily after the deassertion of said reset strobe, thereby permitting the consistent definition of clock phases.