Patent US6090652A successfully refreshed from Google Patents.
US6090652A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device including implanting threshold voltage adjustment ions
Assignee: Hanger Solutions LLC
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Filing: 1997-12-22
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Granted: 2000-07-18
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Expires: 2017-12-22
Abstract
Abstract Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well. Afterward, a P well is formed in the low and high voltage NMOS transistor regions and threshold voltage adjustment ions for low voltage NMOS transistor are then implanted into the P well. Next, a mask pattern exposing the high voltage NMOS transistor region and the low voltage PMOS transistor region is formed on the substrate. Threshold voltage adjustment ions for low voltage PMOS transistor are implanted into the exposed P well of the high voltage NMOS transistor region and the N well of the low voltage PMOS transistor region and the mask pattern is then removed. Next, a first gate insulation film is formed on the substrate and the first gate insulation film existing on the low voltage NMOS and PMOS transistors regions is removed. A second gate insulation film is then formed on the substrate.
Inventors
- 👤 Jae-Kap Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:41
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8314; H10D84/85; H10D84/856
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
236 words
A method of manufacturing a semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other comprising the steps of: providing a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films; forming a N well in the low and high voltage PMOS transistor regions; implanting threshold voltage adjustment ions for high voltage PMOS transistor into the N well; forming a P well in the low and high voltage NMOS transistor regions; implanting threshold voltage adjustment ions for low voltage NMOS transistor into the P well; forming a mask pattern exposing the high voltage NMOS transistor region and the low voltage PMOS transistor region on the substrate; implanting threshold voltage adjustment ions for low voltage PMOS transistor into the exposed P well of the high voltage NMOS transistor region and the N well of the low voltage PMOS transistor region; removing the mask pattern; wherein the steps of implanting threshold voltage adjustment ions for the high voltage PMOS transistor, comprises the steps of: a first implanting of P ions with a first energy and a first concentration and a second implanting of P ions with a second energy which is different from the first energy, and a second concentration which is different from the first concentration.
Claim 2
Independent Claim
236 words
A method of manufacturing a semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other comprising the steps of: providing a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films; forming a N well in the low and high voltage PMOS transistor regions; implanting threshold voltage adjustment ions for high voltage PMOS transistor into the N well; forming a P well in the low and high voltage NMOS transistor regions; implanting threshold voltage adjustment ions for low voltage NMOS transistor into the P well; forming a mask pattern exposing the high voltage NMOS transistor region and the low voltage PMOS transistor region on the substrate; implanting threshold voltage adjustment ions for low voltage PMOS transistor into the exposed P well of the high voltage NMOS transistor region and the N well of the low voltage PMOS transistor region; removing the mask pattern; wherein the steps of implanting threshold voltage adjustment ions for the high voltage PMOS transistor, comprises the steps of: a first implanting of P ions with a first energy and a first concentration and a second implanting of P ions with a second energy which is different from the first energy, and a second concentration which is different from the first concentration.
Claim 3
Dependent Claim
47 words
The method as claimed in claim 1, further comprising the steps of: forming a first gate insulation film on the substrate; removing the first gate insulation film existing on the low voltage NMOS and PMOS transistors regions; and forming a second gate insulation film on the substrate.
Claim 4
Dependent Claim
40 words
The method as claimed in claim 1, wherein the N well is formed by implanting P ions with an energy of 700 KeV to 1.5 MeV and a concentration of 1.sup.× 10 13 to 5.sup.× 10 13 ions/cm 2 .
Claim 5
Dependent Claim
78 words
The method as claimed in claim 1, wherein the step of implanting threshold voltage adjustment ions for high voltage PMOS transistor, comprises the steps of a first implanting P ions with an energy of 180 to 250 KeV and a concentration of 5.sup.× 10 12 to 2.sup.× 10 13 ions/cm 2 and a second implanting P ions with energy of 30 to 80 KeV and a concentration of 5.sup.× 10 11 to 5.sup.× 10 12 ions/cm 2 .
Claim 6
Dependent Claim
39 words
The method as claimed in claim 1, wherein the P well is formed by implanting B ions with an energy of 500 to 700 KeV, and a concentration of 1.sup.× 10 13 to 5.sup.× 10 13 ions/cm 2 .
Claim 7
Dependent Claim
78 words
The method as claimed in claim 1, wherein the step of implanting threshold voltage adjustment ions for low voltage NMOS transistor comprises the steps of a first implanting B ions with an energy of 70 to 120 KeV and a concentration of 5.sup.× 10 12 to 2.sup.× 10 13 ions/cm 2 and a second implanting B ions with energy of 10 to 30 KeV and a concentration of 1.sup.× 10 12 to 5.sup.× 10 12 ions/cm 2 .
Claim 8
Dependent Claim
49 words
The method as claimed in claim 1, wherein the step of implanting threshold voltage adjustment ions for low voltage PMOS transistor is performed by implanting P ions with an energy of 30 to 80 KeV and a concentration of 1.sup.× 10 12 to 8.sup.× 10 12 ions/cm 2 .
Claim 9
Independent Claim
236 words
A method of manufacturing a semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other comprising the steps of: providing a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films; forming a N well in the low and high voltage PMOS transistor regions; implanting threshold voltage adjustment ions for low voltage PMOS transistor into the N well; forming a P well in the low and high voltage NMOS transistor regions; implanting threshold voltage adjustment ions for high voltage NMOS transistor into the P well; forming a mask pattern exposing the low voltage NMOS transistor region and the high voltage PMOS transistor region on the substrate; implanting threshold voltage adjustment ions for low voltage NMOS transistor into the exposed P well of the low voltage NMOS transistor region and the N well of the high voltage PMOS transistor region; removing the mask pattern; wherein the steps of implanting threshold voltage adjustment ions for the high voltage PMOS transistor, comprises the steps of: a first implanting of P ions with a first energy and a first concentration and a second implanting of P ions with a second energy which is different from the first energy, and a second concentration which is different from the first concentration.
Claim 10
Independent Claim
236 words
A method of manufacturing a semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other comprising the steps of: providing a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films; forming a N well in the low and high voltage PMOS transistor regions; implanting threshold voltage adjustment ions for low voltage PMOS transistor into the N well; forming a P well in the low and high voltage NMOS transistor regions; implanting threshold voltage adjustment ions for high voltage NMOS transistor into the P well; forming a mask pattern exposing the low voltage NMOS transistor region and the high voltage PMOS transistor region on the substrate; implanting threshold voltage adjustment ions for low voltage NMOS transistor into the exposed P well of the low voltage NMOS transistor region and the N well of the high voltage PMOS transistor region; removing the mask pattern; wherein the steps of implanting threshold voltage adjustment ions for the high voltage PMOS transistor, comprises the steps of: a first implanting of P ions with a first energy and a first concentration and a second implanting of P ions with a second energy which is different from the first energy, and a second concentration which is different from the first concentration.
Claim 11
Dependent Claim
47 words
The method as claimed in claim 8, further comprising the steps of: forming a first gate insulation film on the substrate; removing the first gate insulation film existing on the low voltage NMOS and PMOS transistor regions; and forming a second gate insulation film on the substrate.
Claim 12
Dependent Claim
40 words
The method as claimed in claim 8, wherein the N well is formed by implanting P ions with an energy of 700 KeV to 1.5 MeV and a concentration of 1.sup.× 10 13 to 5.sup.× 10 13 ions/cm 2 .
Claim 13
Dependent Claim
79 words
The method as claimed in claim 8, wherein the step of implanting threshold voltage adjustment ions for low voltage PMOS transistor, comprises the steps of a first implanting P ions with an energy of 180 to 250 KeV and a concentration of 5.sup.× 10 12 to 2.sup.× 10 13 ions/cm 2 and a second implanting P ions with an energy of 30 to 80 KeV and a concentration of 2.sup.× 10 12 to 8.sup.× 10 12 ions/cm 2 .
Claim 14
Dependent Claim
39 words
The method as claimed in claim 8, wherein the P well is formed by implanting B ions with an energy of 500 to 700 KeV and a concentration of 1.sup.× 10 13 to 5.sup.× 10 13 ions/cm 2 .
Claim 15
Dependent Claim
49 words
The method as claimed in claim 8, wherein the step of implanting threshold voltage adjustment ions for high voltage NMOS transistor is performed by implanting B ions with an energy of 70 to 120 KeV and a concentration of 5.sup.× 10 12 to 2.sup.× 10 13 ions/cm 2 .
Claim 16
Dependent Claim
79 words
The method as claimed in claim 8, wherein the step of implanting threshold voltage adjustment ions for high voltage NMOS transistor, comprises the steps of a first implanting B ions with an energy of 70 to 120 KeV and a concentration of 5.sup.× 10 12 to 2.sup.× 10 13 ions/cm 2 and a second implanting B ions with an energy of 10 to 30 KeV and a concentration of 2.sup.× 10 11 to 3.sup.× 10 12 ions/cm 2 .
Claim 17
Dependent Claim
49 words
The method as claimed in claim 8, wherein the step of implanting threshold voltage adjustment ions for low voltage NMOS transistors is performed by implanting B ions with an energy of 10 to 30 KeV and a concentration of 1.sup.× 10 12 to 5.sup.× 10 12 ions/cm 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |