US6072713A
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Data storage circuit using shared bit line and method therefor
Assignee: Philips Semiconductors Inc
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Filing: 1998-02-04
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Granted: 2000-06-06
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Expires: 2018-02-04
Abstract
Abstract An integrated circuit includes a memory array implemented with as few as two transistors, and four access lines per cell. The array includes row lines and bit lines, with the internally-arranged bit lines shared by two adjacent cells. According to one embodiment, each memory cell includes a first transistor-based circuit in a first cell that is arranged to store information received over a corresponding one of the bit lines, and a second transistor-based circuit in a second cell that is arranged to output information over the same corresponding bit line.
Inventors
- 👤 Vern McKenny
- 👤 James A. Cunningham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:35
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
84 words
A semiconductor memory array comprising: a plurality of read row lines; a plurality of write row lines; and a plurality of adjacent memory cells, each adjacent memory cell including a plurality of MOS type transistors and including first and second memory cells respectively located in one row and in immediately-adjacent columns that include a bit line between the first and second memory cells, the bit line being adapted for writing to the first memory cell and adapted for reading from the second memory cell.
Claim 2
Dependent Claim
84 words
A semiconductor memory array comprising: a plurality of read row lines; a plurality of write row lines; and a plurality of adjacent memory cells, each adjacent memory cell including a plurality of MOS type transistors and including first and second memory cells respectively located in one row and in immediately-adjacent columns that include a bit line between the first and second memory cells, the bit line being adapted for writing to the first memory cell and adapted for reading from the second memory cell.
Claim 3
Dependent Claim
27 words
A semiconductor memory array, according to claim 1, wherein each of the first memory cell and the second memory cell includes at least two MOS type transistors.
Claim 4
Dependent Claim
38 words
A semiconductor memory array, according to claim 2, wherein one of the two transistors is a write transistor and the other of said two transistors is a read transistor having a gate coupled to a data storage node.
Claim 5
Dependent Claim
22 words
A semiconductor memory array, according to claim 2, wherein each of the first and second memory cells include means for storing information.
Claim 6
Dependent Claim
47 words
A semiconductor memory array, according to claim 1, wherein the first and second memory cells are a subset of a multitude of cells configured and arranged to store information and to have the stored information read according to access by one of the plurality of row lines.
Claim 7
Dependent Claim
78 words
A semiconductor memory array, according to claim 5, wherein the first and second memory cells are located immediately-adjacent one another on opposite sides of said bit line, and wherein another bit line is located on one side of the array and is not used for reading information from any cell in the array, and another bit line is located on another side of the array and is not used for writing information to any cell in the array.
Claim 8
Dependent Claim
29 words
A semiconductor memory array, according to claim 1, wherein the first memory cell and the second memory cell are located immediately-adjacent one another on opposite sides of said bit-line.
Claim 9
Dependent Claim
121 words
An integrated circuit, comprising: a plurality of row lines; a plurality of bit-lines; access circuitry coupled to the plurality of row lines and the plurality of bit-lines; and a semiconductor array of memory cells arranged to be accessed in response to the access circuitry and to levels established on certain ones of the row and bit lines, the memory cells including a first transistor-based circuit in a first cell arranged to store information received over a corresponding one of the bit lines, a second transistor-based circuit in a second cell arranged to output information over said corresponding one of the bit lines, wherein the first and second cells are in immediately-adjacent columns that include said corresponding one of the bit lines.
Claim 10
Dependent Claim
121 words
An integrated circuit, comprising: a plurality of row lines; a plurality of bit-lines; access circuitry coupled to the plurality of row lines and the plurality of bit-lines; and a semiconductor array of memory cells arranged to be accessed in response to the access circuitry and to levels established on certain ones of the row and bit lines, the memory cells including a first transistor-based circuit in a first cell arranged to store information received over a corresponding one of the bit lines, a second transistor-based circuit in a second cell arranged to output information over said corresponding one of the bit lines, wherein the first and second cells are in immediately-adjacent columns that include said corresponding one of the bit lines.
Claim 11
Dependent Claim
25 words
An integrated circuit, according to claim 8, wherein each of the first and second transistor-based circuits includes two transistors electrically interconnected at a storage node.
Claim 12
Dependent Claim
18 words
An integrated circuit, according to claim 9, wherein the storage node includes means for enhancing a charge thereat.
Claim 13
Dependent Claim
20 words
An integrated circuit, according to claim 9 wherein the storage node does not include means for enhancing a charge thereat.
Claim 14
Dependent Claim
70 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, a method of accessing data in selected cells, comprising: writing data to a selected cell in a first column using a bit line; and reading data from a selected cell in a second immediately-adjacent column using the same bit line, wherein the first and second columns include the bit line.
Claim 15
Dependent Claim
70 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, a method of accessing data in selected cells, comprising: writing data to a selected cell in a first column using a bit line; and reading data from a selected cell in a second immediately-adjacent column using the same bit line, wherein the first and second columns include the bit line.
Claim 16
Dependent Claim
76 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, an arrangement for storing and retrieving data in selected cells, comprising: means for writing data to a selected cell in a first column using a bit line; and means for reading data from a selected cell in a second immediately-adjacent column using the same bit line, wherein the first and second columns include the bit line.
Claim 17
Dependent Claim
76 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, an arrangement for storing and retrieving data in selected cells, comprising: means for writing data to a selected cell in a first column using a bit line; and means for reading data from a selected cell in a second immediately-adjacent column using the same bit line, wherein the first and second columns include the bit line.
Claim 18
Dependent Claim
99 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, an arrangement for storing and retrieving data in selected cells, comprising: a first transistor-based cell in a first column having a storage node and connecting to a first bit line for outputting stored data and connecting to a second bit line for receiving data; and a second transistor-based cell in a second immediately-adjacent column having a storage node and connecting to the first bit line for receiving data and connecting to a third bit line for outputting stored data.
Claim 19
Dependent Claim
99 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, an arrangement for storing and retrieving data in selected cells, comprising: a first transistor-based cell in a first column having a storage node and connecting to a first bit line for outputting stored data and connecting to a second bit line for receiving data; and a second transistor-based cell in a second immediately-adjacent column having a storage node and connecting to the first bit line for receiving data and connecting to a third bit line for outputting stored data.
Claim 20
Dependent Claim
40 words
An arrangement for storing and retrieving data in selected cells, according to claim 14, where each of the first and second transistor-based cells is implemented using a write NMOS transistor and a read NMOS transistor interconnected at a storage node.
Claim 21
Dependent Claim
85 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, an arrangement for storing and retrieving data in selected cells, comprising: first means in a first column connecting to a first bit line for outputting stored data and connecting to a second bit line for receiving data; and second means in a second immediately-adjacent column connecting to the first bit line for receiving data and connecting to a third bit line for outputting stored data.
Claim 22
Dependent Claim
85 words
For use in a memory array partly defined by a plurality of row lines and a plurality of bit lines, an arrangement for storing and retrieving data in selected cells, comprising: first means in a first column connecting to a first bit line for outputting stored data and connecting to a second bit line for receiving data; and second means in a second immediately-adjacent column connecting to the first bit line for receiving data and connecting to a third bit line for outputting stored data.
Claim 23
Dependent Claim
33 words
An arrangement for storing and retrieving data in selected cells, according to claim 16, wherein said first means and said second means are arranged and configured within their respective cells substantially the same.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |