US3761899A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory with a secondary source voltage to reduce injection
Assignee: STMicroelectronics lnc USA
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Filing: 1971-12-02
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Granted: 1973-09-25
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Expires: 1991-12-02
Abstract
Abstract Dynamic random access memory utilizing MOSFET transistors formed on a single semiconductor chip is described. The integrated circuit has internal circuits, including storage cells arrayed in rows and columns, and interface circuits, including address decoders, etc., for connecting the internal circuits to control circuitry external of the integrated circuit. A primary drain voltage terminal and a primary source voltage terminal are provided for the integrated circuit and are used for the interface circuit. Circuit means formed on the chip establishes a secondary source voltage that is nearer the primary drain voltage than the primary source voltage. The secondary source voltage is used for the internal circuits and reduces loss of data due to injection from the internal circuits.
Inventors
- 👤 Kenny V Mc
- 👤 R Donnely
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/406; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
133 words
The integrated circuit comprising: a plurality of field effect transistors interconnected to form a dynamic data system having a plurality of data interface circuIts requiring drain and source voltages and a plurality of internal circuits requiring drain and source voltages, a drain voltage terminal for the integrated circuit, a source voltage terminal for the integrated circuit, means connecting the drain voltage terminal and the source voltage terminal to the data interface circuits to provide drain and source voltages for the data interface circuits, means connecting the drain voltage terminal to the internal circuits to provide drain voltage for the internal circuits, and circuit means for reducing injection including a resistance connecting the source voltage terminal to the internal circuits to provide a source voltage for the internal circuits significantly nearer the drain voltage.
Claim 2
Dependent Claim
133 words
The integrated circuit comprising: a plurality of field effect transistors interconnected to form a dynamic data system having a plurality of data interface circuIts requiring drain and source voltages and a plurality of internal circuits requiring drain and source voltages, a drain voltage terminal for the integrated circuit, a source voltage terminal for the integrated circuit, means connecting the drain voltage terminal and the source voltage terminal to the data interface circuits to provide drain and source voltages for the data interface circuits, means connecting the drain voltage terminal to the internal circuits to provide drain voltage for the internal circuits, and circuit means for reducing injection including a resistance connecting the source voltage terminal to the internal circuits to provide a source voltage for the internal circuits significantly nearer the drain voltage.
Claim 3
Dependent Claim
94 words
The integrated circuit comprising: a plurality of field effect transistors interconnected to form a data processing system, a drain voltage terminal for the integrated circuit coupled to supply a drain voltage to the data processing system, a source voltage terminal for the integrated circuit connected to the integrated circuit substrate, and circuit means for reducing injection formed within the integrated circuit including a resistive path connecting the source nodes of a plurality of transistors to the source voltage terminal to provide a source voltage internal of the integrated circuit significantly nearer the drain voltage.
Claim 4
Dependent Claim
94 words
The integrated circuit comprising: a plurality of field effect transistors interconnected to form a data processing system, a drain voltage terminal for the integrated circuit coupled to supply a drain voltage to the data processing system, a source voltage terminal for the integrated circuit connected to the integrated circuit substrate, and circuit means for reducing injection formed within the integrated circuit including a resistive path connecting the source nodes of a plurality of transistors to the source voltage terminal to provide a source voltage internal of the integrated circuit significantly nearer the drain voltage.
Claim 5
Dependent Claim
170 words
The memory system formed of FET transistors on a common semiconductor substrate comprising: a plurality of dynamic storage cells arranged in a plurality of rows and columns, a data line for each column of storage cells, at least one address line for each row of storage cells extending transversely of the data lines, the address lines and the data lines being capacitively coupled by stray capacitance, each dynamic storage cell comprising a voltage storage node capacitively coupled to a source supply voltage, a FET write transistor coupling the storage node to the data line and controlled by the respective write line, first and second FET read transistors connected in series and coupling the respective data line to a secondary source supply voltage line, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage nodes, and the secondary source supply voltage line being connected through a resistive path to the substrate supply voltage to reduce injection.
Claim 6
Dependent Claim
170 words
The memory system formed of FET transistors on a common semiconductor substrate comprising: a plurality of dynamic storage cells arranged in a plurality of rows and columns, a data line for each column of storage cells, at least one address line for each row of storage cells extending transversely of the data lines, the address lines and the data lines being capacitively coupled by stray capacitance, each dynamic storage cell comprising a voltage storage node capacitively coupled to a source supply voltage, a FET write transistor coupling the storage node to the data line and controlled by the respective write line, first and second FET read transistors connected in series and coupling the respective data line to a secondary source supply voltage line, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage nodes, and the secondary source supply voltage line being connected through a resistive path to the substrate supply voltage to reduce injection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |