Abstract A dynamic random access memory utilizing MOSFET transistors formed on a single semi-conductor chip is described. The random access memory utilizes 1,024 binary storage cells arrayed in rows and columns. Each row of cells has a read line and a write line. Each column of cells has one data line used for both read and write functions. Each cell is comprised of a write transistor and a pair of read transistors. The write transistor couples a capacitive storage node to the data line and is controlled by the write line. The read transistors are connected in series between the data line and VSS, and one is controlled by the read line and the other is controlled by the voltage on the storage node. A sense amplifier is provided for each data line and is used to apply data through the write transistor to the storage node, and to sense the state of the second read transistor controlled by the data stored on the storage node. The chip includes row and column address means for selecting a particular cell for either read or write mode. The chip also includes a number of features to prevent bipolar injection caused by forward biasing a PN junction as a result of capacitive coupling between various nodes in the circuit, and other features which prevent the loss of data from the storage node.
In a digital data processing integrated circuit utilizing field effect transistors and having a substitute supply voltage and having at least two lines which carry logic levels and which may be capacitively coupled, the improvement comprising circuit means connecting each of the lines to the substrate supply voltage through a common resistive path when both lines are to be at the logic level nearer the substrate supply voltage to thereby reduce transient voltages caused by such capacitive coupling which might cause injection.
Claim 2
Dependent Claim
82 words
In a digital data processing integrated circuit utilizing field effect transistors and having a substitute supply voltage and having at least two lines which carry logic levels and which may be capacitively coupled, the improvement comprising circuit means connecting each of the lines to the substrate supply voltage through a common resistive path when both lines are to be at the logic level nearer the substrate supply voltage to thereby reduce transient voltages caused by such capacitive coupling which might cause injection.
Claim 3
Dependent Claim
36 words
The integrated circuit of claim 1 wherein there are a plurality of lines capacitively coupled to at least one common line, and all lines are connected through the common resistive path to the substrate supply voltage.
Claim 4
Dependent Claim
36 words
The integrated circuit of claim 1 wherein one of the lines is a diffused region in the substrate and the other line is a conductive line spaced from the diffused region by a layer of insulation.
Claim 5
Dependent Claim
82 words
The integrated circuit of claim 1 wherein there are a plurality of diffused lines of a first set extending in generally parallel relationship one to the other and a plurality of conductive lines of a second set extending generally parallel one to the other and crossing the lines of the first set and being spaced therefrom by a layer of insulation, the lines of both the first and second sets being connected through the common resistive path to the substrate supPly voltage.