Sense amplifier for high speed memory

Claim 2

In an electronic matrix memory cell system wherein a bit of information in a cell is selectively addressed by an energizing conductor and a responding conductor, a sense amplifier comprising: impedance means electrically connected in circuit with the responding conductor for developing an electrical signal in response to the current from the cell in the responding conductor; output means responsive to the electrical signal developed by said impedance means for generating an increased signal; electronic impedance means electrically connected in parallel with said impedance means for controllably reducing the effective impedance connected in circuit with the responding conductor thereby reducing the transient pulse time due to the interelectrode capacitance between the energizing conductor and the responding conductor; and control means electrically coupled to said electronic impedance means for controlling the operation thereof by electrically inserting said electronic impedance in parallel with said impedance means when the memory cell is addressed and electrically removing said electronic impedance means from said circuit when the transient pulse has decayed below a permissible level for activating said output means.

Claim 3

The sense amplifier according to claim 1 wherein said output means is a high gain amplifier for generating an increased voltage signal in response to the signal developed in said impedance means.

Claim 4

The sense amplifier according to claim 1 wherein said electronic impedance means is a field-effect transistor electrically connected in circuit as a resistor.

Claim 5

The sense amplifier according to claim 3 wherein the effective resistance value of said field-effect transistor during conduction is very substantially less than the resistance value of said impedance means.

Claim 6

The sense amplifier according to claim 3 wherein said control means is a transistorized switch having its output electrode electrically connected to the drain electrode of said transistor and responsive to an electrical signal applied to its base electrode for controlling the conduction of said transistor.

Claim 7

In an electronic matrix memory cell system wherein a bit of information in a cell is selectively addressed by an energizing conductor and a responding conductor, a sense amplifier comprising: impedance means electrically connected in circuit with the responding conductor for developing an electrical signal in response to the current in the responding conductor; output means responsive to the electrical signal developed by said impedance means for generating an increased signal; electronic impedance means electrically connected in parallel with said impedance means for controllably reducing the effective impedance connected in circuit with the responding conductor thereby reducing the transient pulse time due to the interelectrode capacitance between the energizing conductor and the responding conductor; coNtrol means electrically coupled to said electronic impedance means for controlling the operation thereof by inserting said electronic impedance in parallel with said impedance means when the memory cell is addressed and removing said electronic impedance means from said circuit when the transient pulse has decayed below a permissible level for activating said output means; and capacitance means electrically connected in circuit between said electronic impedance and said control means, said capacitance means responsive to said control means when removing said electronic impedance for generating a transient signal of opposite polarity to the transient signal generated by the removal of said electronic impedance means for reducing said last named transient signal to a mullity.

Claim 8

In an electronic matrix memory cell system wherein a bit of information in a cell is selectively addressed by an energizing conductor and a responding conductor, a sense amplifier comprising: impedance means electrically connected in circuit with the responding conductor for developing an electrical signal in response to the current in the responding conductor; output means responsive to the electrical signal developed by said impedance means for generating an increased signal; electronic impedance means electrically connected in parallel with said impedance means for controllably reducing the effective impedance connected in circuit with the responding conductor thereby reducing the transient pulse time due to the interelectrode capacitance between the energizing conductor and the responding conductor; coNtrol means electrically coupled to said electronic impedance means for controlling the operation thereof by inserting said electronic impedance in parallel with said impedance means when the memory cell is addressed and removing said electronic impedance means from said circuit when the transient pulse has decayed below a permissible level for activating said output means; and capacitance means electrically connected in circuit between said electronic impedance and said control means, said capacitance means responsive to said control means when removing said electronic impedance for generating a transient signal of opposite polarity to the transient signal generated by the removal of said electronic impedance means for reducing said last named transient signal to a mullity.

Claim 9

The sense amplifier according to claim 6 wherein said electronic impedance means is a dual gate field-effect transistor, wherein said capacitance means and one end of said impedance means are electrically connected to the drain electrode, the opposite end of said impedance means is electrically connected to the source electrode, and said control means is electrically connected to the first gate electrode.

Claim 10

The sense amplifier according to claim 7 wherein said control means is a transistor electrically connected in a grounded emitter configuration wherein said emitter lead is electrically connected in circuit to the first gate electrode of said field-effect transistor and the collector lead is electrically connected to through said capacitance to the drain electrode of said field-effect transistor, said transistor is driven into conduction by a signal on its base lead for causing said field-effect transistor to go into conduction and said transistor is driven out of conduction after a predetermined period of time for coupling a signal from its collector lead to the drain electrode to reduce the turn off transient of said field-effect transistor due to the interlectrode capacitance between the first gate and the drain electrode of said field-effect transistor.

Claim 11

A memory system comprising: an array of binary information cells, each cell addressable by a row electrode electrically connected to the input of said cell and a column electrode electrically connected to the output of said cell, said electrodes being capacitively coupled to each other; selection means electrically connected to each row electrode respectively for selecting a predetermined row of cells in said array; a first impedance electrically connected to each column electrode respectively and responsive to the current generated by the binary state of a cell energized by said selection means for developing an electrical signal indicating the binary value of said energized cell; said first impedance means electrically connected in series with the capacitive coupling between the energized row electrode and the column electrode; an electronic impedance means electrically connected in a parallel with said first impedance for controllaby reducing the effective impedance connected in electrical series with the capacitive coupling between the energized row electrode and the column electrode; and control means electrically connected to said electronic impedance means for controlling the operation thereof by electrically inserting said electronic impedance means in parallel with said first impedance means when said selection means initially selects a row electrode for reducing the transient charging time of the capacitance due to said capacitive coupling and for electrically removing said impedance a predetermined interval after insertion thereof.

Claim 12

A memory system comprising: an array of binary information cells, each cell addressable by a row electrode electrically connected to the input of said cell and a column electrode electrically connected to the output of said cell, said electrodes being capacitively coupled to each other; selection means electrically connected to each row electrode respectively for selecting a predetermined row of cells in said array; a first impedance electrically connected to each column electrode respectively and responsive to the current generated by the binary state of a cell energized by said selection means for developing an electrical signal indicating the binary value of said energized cell; said first impedance means electrically connected in series with the capacitive coupling between the energized row electrode and the column electrode; an electronic impedance means electrically connected in a parallel with said first impedance for controllaby reducing the effective impedance connected in electrical series with the capacitive coupling between the energized row electrode and the column electrode; and control means electrically connected to said electronic impedance means for controlling the operation thereof by electrically inserting said electronic impedance means in parallel with said first impedance means when said selection means initially selects a row electrode for reducing the transient charging time of the capacitance due to said capacitive coupling and for electrically removing said impedance a predetermined interval after insertion thereof.

Claim 13

The memory system according to claim 9 wherein said array in an array of light activated cells responsive to a source of radiant energy to generate a binary one value and to the absence of said source to generate a binary zero value.

Claim 14

The memory system according to claim 9 wherein said electronic impedance means is an field-effect transistor having its drain electrode electrically connected between said first impedance means and said column electrode, its gate electrode electrically connected to said control means and its source electrode electrically connected to opposite end of said first impedance means.

Claim 15

The memory system according to claim 11 wherein said control means is a transistorized switch wherein said emitter electrode is electrically connected to the gate electrode of said transistor and electrically connected in circuit to a voltage source, said switch controllable through its base electrode for controlling the conduction of said transistor.

Claim 16

The memory system according to claim 12 further including a capacitor electrically coupled between the collector electrode of said control means and the drain electrode of said electronic impedance means and responsive to the turn-on of said control means.

Claim 17

A memory system comprising: an array of binary information cells, each cell addressable by a row electrode electrically connected to the input of said cell and a column electrode electrically connected to the output of said cell, said electrodes are capacitively coupled to each other; selection means electrically connected to each row electrode respectively for selecting a predetermined row of cells in said array; a resistor electrically connected to each column electrode respectively and responsibe to the current generated by the binary state of a cell energized by said selection means for generating an electrical signal indicating the binary value of said energized cells; said resistor electrically connected in series circuit with the interelectrode capacitance between the energized row electrode and the column electrode; a dual gate field-effect transistor electrically functioning as a resistance wherein the second gate electrode is connected to a voltage supply, the drain electrode is electrically connected between said field-effect transistor and the column electrode, the source electrode is electrically connected in circuit to the other end of said field-effect transistor for controllably reducing the effective resistance connected in electrical series with said interelectrode capacitance; a transistorized switch having its output lead electrically connected to the first gate lead of said field-effect transistor and connected to a voltage source and being controlled by an electrical signal applied to its base lead for causing said field-effect transistor to be driven into conduction to reduce its effective resistance thereby reducing the transient time constant associated with the interelectrode capacitance between the selected row electrode and the column electrode when said selection means is activated; and capacitive means electrically connected between the input lead of said switch and the drain electrode of said field-effect transistor for electrically diminishing the transient pulse generated in said field-effect transistor due to the first gate to drain interelectrode capacitance and applied to said resistor when said field-effect transistor is driven out of conduction by said transistorized switch.

Claim 18

A memory system comprising: an array of binary information cells, each cell addressable by a row electrode electrically connected to the input of said cell and a column electrode electrically connected to the output of said cell, said electrodes are capacitively coupled to each other; selection means electrically connected to each row electrode respectively for selecting a predetermined row of cells in said array; a resistor electrically connected to each column electrode respectively and responsibe to the current generated by the binary state of a cell energized by said selection means for generating an electrical signal indicating the binary value of said energized cells; said resistor electrically connected in series circuit with the interelectrode capacitance between the energized row electrode and the column electrode; a dual gate field-effect transistor electrically functioning as a resistance wherein the second gate electrode is connected to a voltage supply, the drain electrode is electrically connected between said field-effect transistor and the column electrode, the source electrode is electrically connected in circuit to the other end of said field-effect transistor for controllably reducing the effective resistance connected in electrical series with said interelectrode capacitance; a transistorized switch having its output lead electrically connected to the first gate lead of said field-effect transistor and connected to a voltage source and being controlled by an electrical signal applied to its base lead for causing said field-effect transistor to be driven into conduction to reduce its effective resistance thereby reducing the transient time constant associated with the interelectrode capacitance between the selected row electrode and the column electrode when said selection means is activated; and capacitive means electrically connected between the input lead of said switch and the drain electrode of said field-effect transistor for electrically diminishing the transient pulse generated in said field-effect transistor due to the first gate to drain interelectrode capacitance and applied to said resistor when said field-effect transistor is driven out of conduction by said transistorized switch.