US3778783A
Expired / Lapsed
US
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Dynamic random access memory
Assignee: STMicroelectronics lnc USA
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Filing: 1971-11-29
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Granted: 1973-12-11
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Expires: 1991-11-29
Abstract
Abstract A dynamic random access memory utilitizing MOSFET transistors formed on a single semi-conductor chip is described. The random access memory utilizes 1024 binary storage cells arrayed in rows and columns. Each row of cells has a read line and a write line. Each column of cells has one data line used for both read and write functions. Each cell is comprised of a write transistor and a pair of read transistors. The write transistor couples a capacitive storage node to the data line and is controlled by the write line. The read transistors are connected in series between the data line and VSS, and one is controlled by the read line and the other is controlled by the voltage on the storage node. A sense amplifier is provided for each data line and is used to apply data through the write transistor to the storage node, and to sense the state of the second read transistor controlled by the data stored on the storage node. The chip includes row and column address means for selecting a particular cell for either read or write mode. The chip also includes a number of features to prevent bipolar injection caused by forward biasing a PN junction as a result of capacitive coupling between various nodes in the circuit, and other features which prevent the loss of data from the storage node.
Inventors
- 👤 R Proebsting
- 👤 V Mckenny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:23
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; G11C11/406; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; H10; H10W; H10W20/00; H10W20/20
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
119 words
The memory system formed as an integrated circuit comprising: a plurality of storage cells arranged in rows and columnS, a data line for each column of storage cells, and a read line and a write line for each row, each storage cell comprisng a voltage storage node capacitively coupled to a source supply voltage, a FET write transistor coupling the storage node to the data line and controlled by the respective write line, first and second FET read transistors connected in series and coupling the respective data line to a source supply voltage, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage node.
Claim 2
Dependent Claim
119 words
The memory system formed as an integrated circuit comprising: a plurality of storage cells arranged in rows and columnS, a data line for each column of storage cells, and a read line and a write line for each row, each storage cell comprisng a voltage storage node capacitively coupled to a source supply voltage, a FET write transistor coupling the storage node to the data line and controlled by the respective write line, first and second FET read transistors connected in series and coupling the respective data line to a source supply voltage, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage node.
Claim 3
Dependent Claim
56 words
The memory system of claim 1 further characterized by: means for turning the write transistor in a selected cell on, and means for charging the data line to the selected cell to a predetermined voltage level to store the voltage level on the storage node of the cell in which the write transistor is turned on.
Claim 4
Dependent Claim
55 words
The memory system of claim 1 further characterized by: means for turning the first read transistor in a selected cell on, and means for applying a signal to the data line associated with the respective cell to determine the condition of the second read transistor to thereby read the data stored on the storage node.
Claim 5
Dependent Claim
108 words
The memory system of claim 3 further characterized by: row address means for selectively and alternatively applying a read or a write signal to the read line or the write line of only one of the rows of storage cells, means active coincident with a signal on a read line for determining the condition of a selected data line to read the data stored on the storage node of a selected cell, and means responsive to a signal on a write line for driving a selected data line to a predetermined level representative of data to write the predetermined level and therefore, the data on the storage node.
Claim 6
Dependent Claim
82 words
The memory system of claim 1 further comprising: row address means for selectively and alternatively applying a read signal or a write signal to the read line or the write line, respectively, of a selected row of storage cells, and means for storing a signal representative of the data stored on each storage cell of the row during the read signals and for rewriting a signal representative of the data back into the storage cells of the row during the write signal.
Claim 7
Dependent Claim
164 words
The integrated circuit memory system comprising: plurality a plurality of dynamic storage cells arranged in a plurality of rows and a plurality of columns, a data line for each column of storage cells, a read line for each row of storage cells for transferring data from each storage cell of the row to the respective data line when activated during a read cycle, a write line for each row of storage cells and transferring data from each data line to the respective storage cell of the row when activated during a write cycle, row address means for enabling the read line and the write line of a selected row, means for activating the enabled read line during a read cycle and the enabled write line during the write cycle, and means for writing, during a write cycle, in at least a portion of the storage cells of the selected row, data representative of data read from the respective cells during the preceding read cycle.
Claim 8
Dependent Claim
164 words
The integrated circuit memory system comprising: plurality a plurality of dynamic storage cells arranged in a plurality of rows and a plurality of columns, a data line for each column of storage cells, a read line for each row of storage cells for transferring data from each storage cell of the row to the respective data line when activated during a read cycle, a write line for each row of storage cells and transferring data from each data line to the respective storage cell of the row when activated during a write cycle, row address means for enabling the read line and the write line of a selected row, means for activating the enabled read line during a read cycle and the enabled write line during the write cycle, and means for writing, during a write cycle, in at least a portion of the storage cells of the selected row, data representative of data read from the respective cells during the preceding read cycle.
Claim 9
Dependent Claim
38 words
The integrated circuit memory of claim 6 wherein the data written in all of the cells of the selected row during the write cycle is representative of data read from the respective cells during the preceding read cycle.
Claim 10
Dependent Claim
30 words
The integrated circuit memory system of claim 6 further characterized by means for outputting data from at least one of the cells of the addressed row during the read cycle.
Claim 11
Dependent Claim
38 words
The integrated circuit memory system of claim 6 further characterized by means for inputting data to at least one of the storage cells of the selected row from circuitry external of the integrated circuit during the write cycle.
Claim 12
Dependent Claim
77 words
The memory system of claim 6 further comprising: a sense amplifier means for each data line for producing inverted digital logic levels at an output in response to voltage levels intermediate the logic levels at the input, the input including a storage capacitance, and means for connecting the input of each amplifier means to the respective sense amplifier during a read-cycle and the output of each amplifier means to the respective sense amplifier during a write cycle.
Claim 13
Dependent Claim
47 words
The memory system of claim 10 further characterized by: column address means for connecting a data input to the input of a selected sense amplifier during a write cycle and for connecting a data output to the output of a selected sense amplifier during a read cycle.
Claim 14
Dependent Claim
144 words
The memory system of claim 10 wherein each sense amplifier means comprises: an input state comprised of a depletion mode first transistor, an enhancement mode second transistor, and an enhancement mode third transistor connected in series between source and drain voltages, the gate and source of the first transistor being common, the gate and drain of the third transistor being common, and the gate of the second transistor being the input for the two voltage levels, and a first output stage comprised of fourth and fifth enhancement mode transistors connected in series between source and drain voltages, the gate of the fourth transistor being connected to the drain of the second transistor, the gate of the fifth transistor being connected to the gate of the second transistor, and the source of the fourth transistor and the drain of the fifth transistor being the output.
Claim 15
Dependent Claim
70 words
The memory system of claim 12 wherein each sense amplifier is further characterized by: a second output stage comprised of sixth and seventh enhancement mode transistors connected in series between the output of the first stage and a source voltage, the gate of the sixth transistor being connected to the drain of the second transistor, the gate of the seventh transistor being connected to the gate of the second transistor.
Claim 16
Dependent Claim
69 words
The memory system of claim 1 wherein the read lines and the write lines are coupled to the data lines by stray capacitances and the read lines, the write lines and the data lines are charged to the logic level nearer the substrate voltage through a common resistance path to the source voltage supply to prevent transient voltage spikes on the lines as a result of the capacitive coupling.
Claim 17
Dependent Claim
123 words
The memory system of claim 14 further characterized by: a plurality of data interface circuits requiring drain and source voltages and a plurality of internal circuits requiring drain and source voltages, a drain voltage terminal for the integrated circuit, a source voltage terminal for the integrated circuit, means connecting the drain voltage terminal and the source voltage terminal to the data interface circuits to provide drain and source voltages for the data interface circuits, means connecting the drain voltage to the internal circuits to provide drain voltage for the internal circuit, and circuit means including a resistance connecting the source voltage terminal to the internal circuits to provide a source voltage for the internal circuits significantly nearer the drain voltage to reduce injection.
Claim 18
Dependent Claim
21 words
The memory system of claim 15 wherein: the second read transistors are connected through the resistance to the source voltage supply.
Claim 19
Dependent Claim
76 words
The memory system of claim 12 wherein: the data lines are connected by the fifth enhancement mode transistor and a resistance to the substrate voltage supply when the data line transition to the logic level nearest the substrate voltage supply, and further characterized by means connecting the read and write lines through the same resistance to the substrate voltage supply when the read and write lines are at the logic level nearest the substrate voltage supply.
Claim 20
Dependent Claim
251 words
The memory system comprising: a plurality of storage cells arranged in a plurality of rows and a plurAlity of columns, a data line for each column of storage cells, a read line and a write line for each row of storage cells, each storage cell comprising a voltage storage node capacitively coupled to a first supply voltage, a write transistor coupling the storage node to the data line and controlled by the respective write line, first and second read transistors connected in series and coupling the respective data line to the first voltage supply, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage node, read-write means providing alternative read and write signals, row address means for selectively applying the read and write signals to the read and write lines of the rows, means for establishing a voltage on each data line during the write signal that is related to the voltage on the respective data line during the preceding read signal, data input means for receiving a data input signal, data output means, and column address means for transferring a signal to the data output means during a read signal that is representative of data from at least one selected data line, and for selectively transferring a signal from the data input means to at least one selected data line during a write signal that is representative of data to be stored in the memory.
Claim 21
Dependent Claim
251 words
The memory system comprising: a plurality of storage cells arranged in a plurality of rows and a plurAlity of columns, a data line for each column of storage cells, a read line and a write line for each row of storage cells, each storage cell comprising a voltage storage node capacitively coupled to a first supply voltage, a write transistor coupling the storage node to the data line and controlled by the respective write line, first and second read transistors connected in series and coupling the respective data line to the first voltage supply, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage node, read-write means providing alternative read and write signals, row address means for selectively applying the read and write signals to the read and write lines of the rows, means for establishing a voltage on each data line during the write signal that is related to the voltage on the respective data line during the preceding read signal, data input means for receiving a data input signal, data output means, and column address means for transferring a signal to the data output means during a read signal that is representative of data from at least one selected data line, and for selectively transferring a signal from the data input means to at least one selected data line during a write signal that is representative of data to be stored in the memory.
Claim 22
Dependent Claim
252 words
The random access memory comprising: a plurality of storage cells arranged in rows and columns, a data line for each column of storage cells, a read line and a write line for each row of storage cells, each storage cell comprising a voltage storage node capacitively coupled to a first supply voltage, a write transistor coupling the storage node to the data line and controlled by the respective write lines, first and second read transistors connected in series and coupling the respective data line to the first voltage supply, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage node, read-write selector means for establishing, in the alternative, read and write signals in response to an input signal, row address means selectively sleectively applying the read and write signals to the read and write lines of the rows, amplifier means for each column line for producing digital output levels in response to voltage levels at the input above and below a reference level, means coupling the input of the amplifier to the data line in response to the read signal and the output of the amplifier to the data line in response to a write signal, data input means for receiving a data input signal, data output means, and column address means for coupling the data input means to the input of a selected amplifier and the output of the selected amplifier to the data output means.
Claim 23
Dependent Claim
252 words
The random access memory comprising: a plurality of storage cells arranged in rows and columns, a data line for each column of storage cells, a read line and a write line for each row of storage cells, each storage cell comprising a voltage storage node capacitively coupled to a first supply voltage, a write transistor coupling the storage node to the data line and controlled by the respective write lines, first and second read transistors connected in series and coupling the respective data line to the first voltage supply, the first read transistor being controlled by the respective read line and the second read transistor being controlled by the voltage stored on the storage node, read-write selector means for establishing, in the alternative, read and write signals in response to an input signal, row address means selectively sleectively applying the read and write signals to the read and write lines of the rows, amplifier means for each column line for producing digital output levels in response to voltage levels at the input above and below a reference level, means coupling the input of the amplifier to the data line in response to the read signal and the output of the amplifier to the data line in response to a write signal, data input means for receiving a data input signal, data output means, and column address means for coupling the data input means to the input of a selected amplifier and the output of the selected amplifier to the data output means.
Claim 24
Dependent Claim
118 words
In an integrated circuit random access memory having a plurality of dynamic binary storage cells arranged in a plurality of rows and a plurality of columns on a common semiconductor substrate, and having a single data line for each column, the method comprising: enabling a selected row of storage cells for reading, reading data from each storage cell of the enabled row by reading from the respective data line, then enabling said selected row of storage cells for writing, and storing a voltage level in at least a portion of the storage cells of said enabled row representative of the data read from the respective storage cells by writing data from the respective data line into the row.
Claim 25
Dependent Claim
118 words
In an integrated circuit random access memory having a plurality of dynamic binary storage cells arranged in a plurality of rows and a plurality of columns on a common semiconductor substrate, and having a single data line for each column, the method comprising: enabling a selected row of storage cells for reading, reading data from each storage cell of the enabled row by reading from the respective data line, then enabling said selected row of storage cells for writing, and storing a voltage level in at least a portion of the storage cells of said enabled row representative of the data read from the respective storage cells by writing data from the respective data line into the row.
Claim 26
Dependent Claim
39 words
The method of claim 20 wherein: the voltage level stored in at least one of the storage cells of the selected rows is representative of data input to the integrated circuit rather than data read from the respective cells.
Claim 27
Dependent Claim
25 words
The method of claim 21 wherein: the voltage level stored in one of the storage cells is representatIve of data input to the integrated circuit.
Claim 28
Dependent Claim
27 words
The method of claim 20 wherein: the data read from at least one of the storage cells of said selected row is output from the integrated circuit.
Claim 29
Dependent Claim
27 words
The method of claim 23 wherein: the data read from a selected one of the storage cells of the selected row is output from the integrated circuit.
Claim 30
Dependent Claim
54 words
The method of claim 20 wherein: the data read from at least one of the storage cells of said selected row is output from the integrated circuit, and the voltage level stored in said at least one of the storage cells of the selected row is representative of data input to the integrated circuit.
Claim 31
Dependent Claim
50 words
The method of claim 25 wherein: the data read from one of the storage cells of said selected row is output from the integrated circuit, and the voltage level stored in said one of the storage cells of the selected row is representative of data input to the integrated circuit.
References Cited (Backward Citations)
US3636528A
Cited
US3593037A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |