US4449142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: NTT Inc
•
Filing: 1981-02-02
•
Granted: 1984-05-15
•
Expires: 2001-02-02
Abstract
Abstract A semiconductor memory device comprises a gate electrode provided via a gate insulating film on a semiconductor layer formed on a substrate and two diffused semiconductor regions provided to form a field effect transistor together with the gate electrode. An electrical charge is supplied to one of the diffused regions from the other region to thereby vary a width of a space charge layer appearing around the one diffused region so that informations "1" and "0" are selectively stored in the device. The stored information is read-out by detecting presence or absence of a buried channel between the space charge layer and the substrate.
Inventors
- 👤 Toshiaki Tsuchiya
- 👤 Manabu Itsumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:45
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H10B; H10B12/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
187 words
A semiconductor memory device comprising: a substrate; a first semiconductor region of a first conductivity type formed on said substrate; a gate insulating film formed on said first semiconductor region; a first gate electrode disposed on said gate insulating film; a second semiconductor region of a second conductivity type formed in said first semiconductor region in relation with an end of said gate electrode; a first charge storage portion formed apart from said second semiconductor region and in relation with the other end of said gate electrode; and means for detecting conductivity of a buried channel formed between said substrate and a space charge layer which is formed in said first semiconductor region in accordance with an amount of electric charge supplied to said charge storage portion, said buried channel detecting means comprising a first external terminal connected to said second semiconductor region and a second external terminal connected to a portion of said first semiconductor region which is opposed to said gate electrode with said charge storage portion interposed therebetween, wherein the junction formed between said first and second semiconductor regions is forward biased during read-out.
Claim 2
Dependent Claim
187 words
A semiconductor memory device comprising: a substrate; a first semiconductor region of a first conductivity type formed on said substrate; a gate insulating film formed on said first semiconductor region; a first gate electrode disposed on said gate insulating film; a second semiconductor region of a second conductivity type formed in said first semiconductor region in relation with an end of said gate electrode; a first charge storage portion formed apart from said second semiconductor region and in relation with the other end of said gate electrode; and means for detecting conductivity of a buried channel formed between said substrate and a space charge layer which is formed in said first semiconductor region in accordance with an amount of electric charge supplied to said charge storage portion, said buried channel detecting means comprising a first external terminal connected to said second semiconductor region and a second external terminal connected to a portion of said first semiconductor region which is opposed to said gate electrode with said charge storage portion interposed therebetween, wherein the junction formed between said first and second semiconductor regions is forward biased during read-out.
Claim 3
Dependent Claim
15 words
A memory device according to claim 1, in which said substrate is an insulator substrate.
Claim 4
Dependent Claim
26 words
A memory device according to claim 2, in which said insulator substrate comprises one selected from a group of silicon oxide, sapphire, spinnel and silicon nitride.
Claim 5
Dependent Claim
20 words
A memory device according to claim 1, in which said substrate is a semiconductor substrate of said second conductivity type.
Claim 6
Dependent Claim
28 words
A memory device according to claim 1, in which said charge storage portion comprises a semiconductor region of said second conductivity type formed in said first semiconductor region.
Claim 7
Dependent Claim
42 words
A memory device according to claim 1, in which said charge storage portion comprises a metal-insulator semiconductor type capacitor having a capacitor electrode provided on said gate insulating film separately from said gate electrode and applied with a certain direct current voltage.
Claim 8
Dependent Claim
49 words
A memory device according to claim 6, in which said charge storage portion further comprises a third semiconductor region of said second conductivity type provided in said first semiconductor region under a portion of said gate insulating film which is interposed between said capacitor electrode and said gate electrode.
Claim 9
Dependent Claim
34 words
A memory device according to claim 6, in which said charge storage portion further comprises an inter-layer insulating film provided on said capacitor electrode, said gate electrode being spreading over said inter-layer insulating film.
Claim 10
Dependent Claim
34 words
A memory device according to claim 6, in which said charge storage portion further comprises an inter-layer insulating film provided on said gate electrode, said capacitor electrode being spreading over said inter-layer insulating film.
Claim 11
Dependent Claim
112 words
A memory device according to claim 1, further comprising a second gate electrode disposed on said gate insulating film to be symmetrical relative to said first electrode with said second semiconductor region being central so that the second gate electrode has one end located in connection with said second semiconductor region, and a second charge storage portion formed in relation with the other end of said second gate electrode wherein said detecting means further detects conductivity of a buried channel formed between said substrate and a space charge layer which is varied in said first semiconductor region in accordance with an amount of electric charge supplied to said second charge storage portion.
Claim 12
Dependent Claim
42 words
A memory device according to claim 10, in which each of said charge storage portions comprises a metal-insulator-semiconductor capacitor having a capacitor electrode provided on said gate insulating film separately from the corresponding gate electrode and applied with a certain constant voltage.
Claim 13
Dependent Claim
53 words
A memory device according to claim 10, in which each of said charge storage portions comprises a third semiconductor region of said second conductivity type provided in said first semiconductor region under a portion of said gate insulating film which is interposed between each ones of said capacitor electrodes and said gate electrodes.
Claim 14
Dependent Claim
30 words
A memory device according to claim 10, in which each of said charge storage portions comprises a semiconductor region of said second conductivity type provided in said first semiconductor region.
References Cited (Backward Citations)
US3639813A
Cited
US3918070A
Cited
US4074302A
Cited
US4161741A
Cited
WO1979000474A1
Cited
US4291391A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-15 | 1987-11-14 | 1988-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-15 | 1991-11-14 | 1992-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-15 | 1995-11-14 | 1996-05-15 | $7700.00 | Window Closed / Lapsed |