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US6067262A
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Redundancy analysis for embedded memories with built-in self test and built-in self repair
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-12-11
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Granted: 2000-05-23
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Expires: 2018-12-11
Abstract
Abstract An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.
Inventors
- 👤 V. Swamy Irrinki
- 👤 Tuan L. Phan
- 👤 William D. Schwarz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:09
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/006; G11C29/04; G11C29/08; G11C29/12; G11C2029/0405; G11C2029/1208; G11C29/56; G11C2029/5604; G11C2029/5606; G11C29/70; G11C29/72
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
121 words
A method for testing integrated circuits having built-in self test and built-in self repair circuitry, comprising the steps of: applying a first stress factor to an integrated circuit die; performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit die; generating first fault information pertaining to any faults detected by the first built-in self test analysis; applying a second stress factor to the integrated circuit die; performing a second built-in self test analysis on the predetermined portion of the integrated circuit die; generating second fault information pertaining to any faults detected by the second built-in self test analysis; and comparing the first fault information with the second fault information to ascertain any differences.
Claim 2
Independent Claim
121 words
A method for testing integrated circuits having built-in self test and built-in self repair circuitry, comprising the steps of: applying a first stress factor to an integrated circuit die; performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit die; generating first fault information pertaining to any faults detected by the first built-in self test analysis; applying a second stress factor to the integrated circuit die; performing a second built-in self test analysis on the predetermined portion of the integrated circuit die; generating second fault information pertaining to any faults detected by the second built-in self test analysis; and comparing the first fault information with the second fault information to ascertain any differences.
Claim 3
Dependent Claim
27 words
The method of claim 1, further comprising the step of rejecting the integrated circuit die if the first fault information does not equal the second fault information.
Claim 4
Dependent Claim
39 words
The method of claim 1, further comprising the step of performing a built-in self repair procedure after generating the first fault information to reconfigure any faulty portions of the integrated circuit die as indicated by the first fault information.
Claim 5
Dependent Claim
22 words
The method of claim 1, wherein the first stress factor is a minimum temperature and second stress factor is a maximum temperature.
Claim 6
Dependent Claim
23 words
The method of claim 1, wherein the first stress factor is a minimum voltage and the second stress factor is a maximum voltage.
Claim 7
Dependent Claim
31 words
The method of claim 1, wherein the first fault information is a first set of memory address locations and the second fault information is a second set of memory address locations.
Claim 8
Dependent Claim
46 words
The method of claim 1, wherein the step of performing a first built-in self test analysis comprises the steps of: generating an initial test pattern via the built-in self test circuitry; and exercising the initial test pattern on the predetermined portion of the integrated circuit die.
Claim 9
Dependent Claim
46 words
The method of claim 7, wherein the step of performing a second built-in self test analysis comprises the steps of: generating a secondary test pattern via the built-in self test circuitry; and exercising the secondary test pattern on the predetermined portion of the integrated circuit die.
Claim 10
Dependent Claim
17 words
The method of claim 8, wherein the initial test pattern and the secondary test pattern are identical.
Claim 11
Dependent Claim
17 words
The method of claim 1, wherein the predetermined portion of the integrated circuit die comprises a memory.
Claim 12
Dependent Claim
14 words
The method of claim 10, wherein the memory is a dynamic random access memory.
Claim 13
Dependent Claim
14 words
The method of claim 10, wherein the memory is a static random access memory.
Claim 14
Independent Claim
174 words
A method for testing integrated circuits with embedded memories and built-in self test and built-in self repair circuitry, comprising the steps of: applying a first stress factor to an integrated circuit die; performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit die; generating first fault information pertaining to any faults detected by the first built-in self test analysis; applying a second stress factor to the integrated circuit die; performing a second built-in self test analysis on the predetermined portion of the integrated circuit die; generating second fault information pertaining to any faults detected by the second built-in self test analysis; applying at least one additional stress factor; performing at least one additional built-in self test analysis on the predetermined portion of the integrated circuit die; generating at least one additional fault information pertaining to any faults detected by the additional built-in test analysis; and comparing the first fault information, the second fault information and the at least one additional fault information to ascertain any differences.
Claim 15
Independent Claim
174 words
A method for testing integrated circuits with embedded memories and built-in self test and built-in self repair circuitry, comprising the steps of: applying a first stress factor to an integrated circuit die; performing a first built-in self test analysis to detect faults in a predetermined portion of the integrated circuit die; generating first fault information pertaining to any faults detected by the first built-in self test analysis; applying a second stress factor to the integrated circuit die; performing a second built-in self test analysis on the predetermined portion of the integrated circuit die; generating second fault information pertaining to any faults detected by the second built-in self test analysis; applying at least one additional stress factor; performing at least one additional built-in self test analysis on the predetermined portion of the integrated circuit die; generating at least one additional fault information pertaining to any faults detected by the additional built-in test analysis; and comparing the first fault information, the second fault information and the at least one additional fault information to ascertain any differences.
Claim 16
Dependent Claim
37 words
The method of claim 13, further comprising the step of rejecting the integrated circuit die if the first fault information, the second fault information or the at least one additional fault information do not equal one another.
Claim 17
Dependent Claim
48 words
The method of claim 13, wherein the first fault information is a first set of memory address locations, the second fault information is a second set of memory address locations and the at least one additional fault information is an least one additional set of memory address locations.
Claim 18
Dependent Claim
46 words
The method of claim 13, wherein the step of performing a first built-in self test analysis comprises the steps of: generating an initial test pattern via the built-in self test circuitry; and exercising the initial test pattern on the predetermined portion of the integrated circuit die.
Claim 19
Dependent Claim
46 words
The method of claim 16, wherein the step of performing a second built-in self test analysis comprises the steps of: generating a secondary test pattern via the built-in self test circuitry; and exercising the secondary test pattern on the predetermined portion of the integrated circuit die.
Claim 20
Dependent Claim
53 words
The method of claim 17, wherein the step of performing an least one additional built-in self test analysis comprises the steps of: generating a least one additional test pattern via the built-in self test circuitry; and exercising the at least one additional test pattern on the predetermined portion of the integrated circuit die.
Claim 21
Dependent Claim
24 words
The method of claim 18, wherein the initial test pattern, the secondary test pattern and the at least one additional test pattern are identical.
Claim 22
Dependent Claim
26 words
The method of claim 18, wherein the initial test pattern, the secondary test pattern and the at least one additional test pattern comprise a march algorithm.
Claim 23
Dependent Claim
27 words
The method of claim 18, the initial test pattern, the secondary test pattern and the at least one additional test pattern comprise a neighbor pattern sensitive algorithm.
Claim 24
Dependent Claim
17 words
The method of claim 13, wherein the predetermined portion of the integrated circuit die comprises a memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |