US5574692A
Expired / Lapsed
US
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Memory testing apparatus for microelectronic integrated circuit
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1995-06-07
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Granted: 1996-11-12
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Expires: 2015-06-07
Abstract
Abstract A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The apparatus includes an input unit for writing test data into the memories, a parallel output bus having a second number of bits which is smaller than the first number of bits, and an output unit for selectively connecting outputs of the memories to the output bus such that a total number of bits of the selected outputs is not greater than the second number of bits. The outputs of the memories are connected to the output unit in groups, and the output unit is configured to selectively connect the groups of outputs to the output bus in response to respective control signals to read test data out of the memories. Data is applied from the memories to the output unit in bytes. For memories that have parallel outputs wider than one byte of data, multiplexers are provided for successively applying the data from the memories to the output unit one byte at a time. Output data is true data, not encrypted to reduce bits and, thusly, observability.
Inventors
- 👤 Gregg Dierke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:31
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G11C29/04; G11C29/08; G11C29/48
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
110 words
A testing apparatus for testing a plurality of memories including parallel outputs having a total of a first number of bits, comprising: a parallel output bus having a second number of bits which is smaller than said first number of bits; output means for selectively connecting outputs of the memories to the parallel output bus such that a total number of bits of said selected outputs is not greater than said second number of bits; and control means for writing test data into the memories; and for controlling the output means to read the test data out of the memories and apply the test data to the parallel output bus.
Claim 2
Dependent Claim
110 words
A testing apparatus for testing a plurality of memories including parallel outputs having a total of a first number of bits, comprising: a parallel output bus having a second number of bits which is smaller than said first number of bits; output means for selectively connecting outputs of the memories to the parallel output bus such that a total number of bits of said selected outputs is not greater than said second number of bits; and control means for writing test data into the memories; and for controlling the output means to read the test data out of the memories and apply the test data to the parallel output bus.
Claim 3
Dependent Claim
50 words
A testing apparatus as in claim 1, in which: the outputs of the memories are connected to the output means in groups; and the output means is configured to selectively connect said groups of outputs to the parallel output bus in response to respective control signals from the control means.
Claim 4
Dependent Claim
43 words
A testing apparatus as in claim 2, in which the output means comprises a multiplexer having data inputs connected to the outputs of the memories, a data output connected to the parallel output bus, and a select input connected to the control means.
Claim 5
Dependent Claim
22 words
A testing apparatus as in claim 1 in which the control means writes said test data to the memories simultaneously in parallel.
Claim 6
Dependent Claim
75 words
A testing apparatus as in claim 1, in which: one of the memories includes a parallel input having a third number of bits; the test data has a fourth number of bits which is smaller than said third number of bits; and the control means comprises circuitry for replicating and concatenating the test data to produce concatenated test data having said third number of bits and applying said concatenated test data to the parallel input.
Claim 7
Dependent Claim
91 words
A testing apparatus as in claim 1, in which: each memory has a parallel input; the testing apparatus further comprises a plurality of input switch means connected to the memories respectively, each switch means having a parallel output connected to the parallel input of the memory, a parallel logic input for receiving logic data and a parallel test input for receiving the test data; and the control means comprises multiplexing means for selectively controlling each input switch means to connect the logic input or the test input to the output thereof.
Claim 8
Dependent Claim
128 words
A testing apparatus as in claim 1, in which: one of the memories includes a parallel output having a third number of bits; the testing apparatus further comprises output switch means having a parallel input connected to the parallel output of said one of the memories, and a parallel output having a fourth number of bits which is less than said third number of bits which is connected to the output means; the output switch means comprises means for selectively connecting groups of outputs of said one of the memories to the output means such that each group has said third number of bits; and the control means comprises multiplexing means for controlling the output switch means to sequentially connect said groups of outputs to the output means.
Claim 9
Dependent Claim
21 words
A testing apparatus as in claim 7, in which each group of outputs corresponds to a byte of said test data.
Claim 10
Dependent Claim
16 words
A testing apparatus as in claim 8, in which the output switch means comprises a multiplexer.
Claim 11
Dependent Claim
115 words
A microelectronic circuit, comprising: a plurality of memories including parallel outputs having a total of a first number of bits, comprising: a parallel output bus having a second number of bits which is smaller than said first number of bits; output means for selectively connecting outputs of the memories to the parallel output bus such that a total number of bits of said selected outputs is not greater than said second number of bits; input means for inputting test data; and control means for writing test data into the memories; and for controlling the output means to read the test data out of the memories and apply the test data to the parallel output bus.
Claim 12
Dependent Claim
115 words
A microelectronic circuit, comprising: a plurality of memories including parallel outputs having a total of a first number of bits, comprising: a parallel output bus having a second number of bits which is smaller than said first number of bits; output means for selectively connecting outputs of the memories to the parallel output bus such that a total number of bits of said selected outputs is not greater than said second number of bits; input means for inputting test data; and control means for writing test data into the memories; and for controlling the output means to read the test data out of the memories and apply the test data to the parallel output bus.
Claim 13
Dependent Claim
50 words
A microelectronic circuit as in claim 10, in which: the outputs of the memories are connected to the output means in groups; and the output means is configured to selectively connect said groups of outputs to the parallel output bus in response to respective control signals from the control means.
Claim 14
Dependent Claim
43 words
A microelectronic circuit as in claim 11, in which the output means comprises a multiplexer having data inputs connected to the outputs of the memories, a data output connected to the parallel output bus and a select input connected to the control means.
Claim 15
Dependent Claim
22 words
A microelectronic circuit as in claim 10, in which the control means writes said test data to the memories simultaneously in parallel.
Claim 16
Dependent Claim
75 words
A microelectronic circuit as in claim 10, in which: one of the memories includes a parallel input having a third number of bits; the test data has a fourth number of bits which is smaller than said third number of bits; and the control means comprises circuitry for replicating and concatenating the test data to produce concatenated test data having said third number of bits and applying said concatenated test data to the parallel input.
Claim 17
Dependent Claim
99 words
A microelectronic circuit as in claim 10, further comprising logic circuitry, in which: each memory has a parallel input; the microelectronic circuit further comprises a plurality of input switch means connected to the memories respectively, each switch means having a parallel output connected to the parallel input of the memory, a parallel logic input for receiving logic data from the logic circuitry and a parallel test input for receiving the test data; and the control means comprises multiplexing means for selectively controlling each input switch means to connect the logic input or the test input to the output thereof.
Claim 18
Dependent Claim
128 words
A microelectronic circuit as in claim 10, in which: one of the memories includes a parallel output having a third number of bits; the microelectronic circuit further comprises output switch means having a parallel input connected to the parallel output of said one of the memories, and a parallel output having a fourth number of bits which is less than said third number of bits which is connected to the output means; the output switch means comprises means for selectively connecting groups of outputs of said one of the memories to the output means such that each group has said third number of bits; and the control means comprises multiplexing means for controlling the output switch means to sequentially connect said groups of outputs to the output means.
Claim 19
Dependent Claim
21 words
A microelectronic circuit as in claim 16, in which each group of outputs corresponds to a byte of said test data.
Claim 20
Dependent Claim
16 words
A testing apparatus as in claim 17, in which the output switch means comprises a multiplexer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |