US5761489A
Expired / Lapsed
US
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Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory system
Assignee: NXP USA Inc
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Filing: 1995-04-17
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Granted: 1998-06-02
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Expires: 2015-04-17
Abstract
Abstract A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.
Inventors
- 👤 James L. Broseghini
- 👤 John A. Langan
- 👤 Thomas J. Poterek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
127 words
An integrated circuit having an apparatus for performing scan testing of a plurality of circuits, the apparatus comprising: a plurality of circuits to be scan tested; first circuitry generating a data string for a scan test; a memory system coupled to the first circuitry wherein in a first mode of operation, the memory system stores the data string, in a second mode of operation, the memory system outputs a portion of the data string, and in a third mode, the memory system stores data or instructions for use by the integrated circuit; and a plurality of Scan-input latches for serially receiving the data string output from the memory system in the second mode, the plurality of Scan-input latches coupled to the plurality of circuits to be tested.
Claim 2
Dependent Claim
127 words
An integrated circuit having an apparatus for performing scan testing of a plurality of circuits, the apparatus comprising: a plurality of circuits to be scan tested; first circuitry generating a data string for a scan test; a memory system coupled to the first circuitry wherein in a first mode of operation, the memory system stores the data string, in a second mode of operation, the memory system outputs a portion of the data string, and in a third mode, the memory system stores data or instructions for use by the integrated circuit; and a plurality of Scan-input latches for serially receiving the data string output from the memory system in the second mode, the plurality of Scan-input latches coupled to the plurality of circuits to be tested.
Claim 3
Dependent Claim
144 words
The apparatus of claim 1, wherein the memory system comprises: a shift register serially receiving the data string from the first circuitry and periodically outputting N bits in the first mode, where N is an integer; a counter generating a first series of sequential addresses responsive to a number of received bits of the data string in the first mode and generating a second series of sequential addresses responsive to a number of bits outputted by the memory system in the second mode; and a memory array periodically storing the N bits outputted by the shift register at one of the first series of sequential addresses in the first modes outputting N bits indexed by one of the second series of sequential addresses as the portion of the data string in the second mode, and binarily indexing data or instructions in the third mode.
Claim 4
Dependent Claim
26 words
The apparatus of claim 2, further comprising a plurality of Scan-output latches, the plurality of Scan-output latches coupled to the plurality of circuits to be tested.
Claim 5
Dependent Claim
20 words
The apparatus of claim 3, wherein an output of the plurality of Scan-output latches is coupled to the first circuitry.
Claim 6
Dependent Claim
14 words
The apparatus of claim 3, further comprising an arithmetic logic unit for executing instructions.
Claim 7
Dependent Claim
26 words
The apparatus of claim 1, further comprising a plurality of Scan-output latches, the plurality of Scan-output latches coupled to the plurality of circuits to be tested.
Claim 8
Dependent Claim
20 words
The apparatus of claim 6, wherein an output of the plurality of Scan-output latches is coupled to the first circuitry.
Claim 9
Dependent Claim
14 words
The apparatus of claim 6, further comprising an arithmetic logic unit for executing instructions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |