US5663967A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Defect isolation using scan-path testing and electron beam probing in multi-level high density asics
Assignee: Bell Semiconductor LLC
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Filing: 1995-10-19
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Granted: 1997-09-02
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Expires: 2015-10-19
Abstract
Abstract A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).
Inventors
- 👤 Grant A. Lindberg
- 👤 Sharad Prasad
- 👤 Kaushik De
- 👤 Arun K. Gunda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2257; G01; G01R; G01R31/00; G01R31/28; G01R31/302; G01R31/305; G01R31/307; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G06F11/2273
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
287 words
A method of isolating a defect in an integrated circuit device, comprising the steps of: defining a fault dictionary of faults anticipated from specific scan patterns applied to a design simulation of an integrated circuit device using scan test vectors which are included in said fault dictionary said faults included predefined faults and failures from the design simulation of the integrated circuit device; testing the integrated circuit device with said scan test vectors; collecting outputs from the integrated circuit device, the outputs generated by said scan test vectors testing the integrated circuit device; mapping said scan test vectors, which cause incorrect outputs from the integrated circuit device, with corresponding ones of said outputs from the integrated circuit device into simulation scan patterns; performing, in response to said simulation scan patterns, a scan integrity test of sequential circuitry defining a scan chain in the integrated circuit device and, if the scan integrity test fails, probing the scan chain to isolate the fault; if the scan integrity test passes, providing said simulation scan patterns to a diagnostic software program simulator; creating, by said diagnostic software program simulator, a list of suspect faults in combinational logic of the integrated circuit device, based on said simulation scan patterns, to localize possible fault candidates in the integrated circuit device; if the list of suspect faults is sufficiently small, probing a selected area of the combinational logic of the integrated circuit device to determine the location of the fault in the combinational logic; if the list of suspect faults is not sufficiently small, creating additional scan test vectors so as to further localize possible fault candidates in the integrated circuit device; and retesting the integrated circuit device with said additional scan test vectors.
Claim 2
Independent Claim
287 words
A method of isolating a defect in an integrated circuit device, comprising the steps of: defining a fault dictionary of faults anticipated from specific scan patterns applied to a design simulation of an integrated circuit device using scan test vectors which are included in said fault dictionary said faults included predefined faults and failures from the design simulation of the integrated circuit device; testing the integrated circuit device with said scan test vectors; collecting outputs from the integrated circuit device, the outputs generated by said scan test vectors testing the integrated circuit device; mapping said scan test vectors, which cause incorrect outputs from the integrated circuit device, with corresponding ones of said outputs from the integrated circuit device into simulation scan patterns; performing, in response to said simulation scan patterns, a scan integrity test of sequential circuitry defining a scan chain in the integrated circuit device and, if the scan integrity test fails, probing the scan chain to isolate the fault; if the scan integrity test passes, providing said simulation scan patterns to a diagnostic software program simulator; creating, by said diagnostic software program simulator, a list of suspect faults in combinational logic of the integrated circuit device, based on said simulation scan patterns, to localize possible fault candidates in the integrated circuit device; if the list of suspect faults is sufficiently small, probing a selected area of the combinational logic of the integrated circuit device to determine the location of the fault in the combinational logic; if the list of suspect faults is not sufficiently small, creating additional scan test vectors so as to further localize possible fault candidates in the integrated circuit device; and retesting the integrated circuit device with said additional scan test vectors.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein the step of probing the integrated circuit device is done with an electron beam prober.
Claim 4
Dependent Claim
297 words
An integrated circuit device defect isolation testing apparatus, comprising: means for storing a fault dictionary of faults anticipated from specific scan patterns applied to a design simulation of an integrated circuit device, including predefined faults and failures from the design simulation of the integrated circuit device using said scan test vectors; means for testing the integrated circuit device with said scan test vectors from said fault dictionary; means for collecting outputs from the integrated circuit device, the outputs generated by said scan test vectors testing the integrated circuit device; means for mapping said scan test vectors, which cause incorrect outputs from the integrated circuit device, with corresponding ones of said outputs from the integrated circuit device into simulation scan patterns; means for performing, in response to said simulation scan patterns, a scan integrity test of sequential circuitry defining a scan chain in the integrated circuit device and, if the scan integrity test fails, means for probing the scan chain to isolate the fault; if the scan integrity test passes, providing said simulation scan patterns to a diagnostic software program simulator; means for creating, by said diagnostic software program simulator, a list of suspect faults in combinational logic of the integrated circuit device based on said simulation scan patterns to localize possible fault candidates in the integrated circuit device; if the list of suspect faults is sufficiently small, means for probing a selected area of the combinational logic of the integrated circuit device to determine the location of the fault in the combinational logic; if the list of suspect faults is not sufficiently small, means for creating additional scan test vectors so as to further localize possible fault candidates in the integrated circuit device; and means for retesting the integrated circuit device with said additional scan test vectors.
Claim 5
Dependent Claim
297 words
An integrated circuit device defect isolation testing apparatus, comprising: means for storing a fault dictionary of faults anticipated from specific scan patterns applied to a design simulation of an integrated circuit device, including predefined faults and failures from the design simulation of the integrated circuit device using said scan test vectors; means for testing the integrated circuit device with said scan test vectors from said fault dictionary; means for collecting outputs from the integrated circuit device, the outputs generated by said scan test vectors testing the integrated circuit device; means for mapping said scan test vectors, which cause incorrect outputs from the integrated circuit device, with corresponding ones of said outputs from the integrated circuit device into simulation scan patterns; means for performing, in response to said simulation scan patterns, a scan integrity test of sequential circuitry defining a scan chain in the integrated circuit device and, if the scan integrity test fails, means for probing the scan chain to isolate the fault; if the scan integrity test passes, providing said simulation scan patterns to a diagnostic software program simulator; means for creating, by said diagnostic software program simulator, a list of suspect faults in combinational logic of the integrated circuit device based on said simulation scan patterns to localize possible fault candidates in the integrated circuit device; if the list of suspect faults is sufficiently small, means for probing a selected area of the combinational logic of the integrated circuit device to determine the location of the fault in the combinational logic; if the list of suspect faults is not sufficiently small, means for creating additional scan test vectors so as to further localize possible fault candidates in the integrated circuit device; and means for retesting the integrated circuit device with said additional scan test vectors.
Claim 6
Dependent Claim
15 words
The apparatus of claim 3, wherein the means for probing is an electron beam prober.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |