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US5068547A
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Process monitor circuit
Assignee: LSI Corp
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Filing: 1990-09-05
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Granted: 1991-11-26
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Expires: 2010-09-05
Abstract
Abstract In accordance with the present invention, a process monitor circuit and a method for monitoring a process are provided. The process monitor circuit provides first and second logic paths, the first logic path having a delay sensitive to whether the input logic transition is from logic high to logic low, or from logic low to logic high. The second logic path has substantially equal delays for either logic state transition. The two differences in delay between the first and second logic paths under the two logic state transitions are used to monitor the process steps for manufacturing the P and N transistors.
Inventors
- 👤 William H. Gascoyne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:36
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
224 words
A process monitor circuit, comprising: a first delay path comprising a plurality of logic gates having an input terminal and a first output terminal, said first delay path providing after a first delay a first logic state transition at said first output terminal, when a first input logic state transition is received at said input terminal, and providing after a second delay a second logic state transition at said first output terminal, when a second input logic state transition opposite said first input logic state transition is received at said input terminal, said first and second delays being distinguishably different; a second delay path having a second output terminal and connected to said input terminal, said second delay path providing after a third delay a third logic state transition at said second output terminal, when said first input logic state transition is received at said input terminal, and providing after a fourth delay a fourth logic state transition at said second output terminal, when said second input logic state transition is received at said input terminal, said third and fourth delays being substantially equal; and means, having a third output terminal and connected to said first and second output terminals, for providing a logic state transition on said third output terminal upon receiving each of said first, second, third and fourth logic state transitions.
Claim 2
Dependent Claim
224 words
A process monitor circuit, comprising: a first delay path comprising a plurality of logic gates having an input terminal and a first output terminal, said first delay path providing after a first delay a first logic state transition at said first output terminal, when a first input logic state transition is received at said input terminal, and providing after a second delay a second logic state transition at said first output terminal, when a second input logic state transition opposite said first input logic state transition is received at said input terminal, said first and second delays being distinguishably different; a second delay path having a second output terminal and connected to said input terminal, said second delay path providing after a third delay a third logic state transition at said second output terminal, when said first input logic state transition is received at said input terminal, and providing after a fourth delay a fourth logic state transition at said second output terminal, when said second input logic state transition is received at said input terminal, said third and fourth delays being substantially equal; and means, having a third output terminal and connected to said first and second output terminals, for providing a logic state transition on said third output terminal upon receiving each of said first, second, third and fourth logic state transitions.
Claim 3
Dependent Claim
22 words
A process monitor circuit as in claim 1, wherein said means for providing a logic state transition comprises an XNOR logic gate.
Claim 4
Dependent Claim
22 words
A process monitor circuit as in claim 1, wherein said means for providing a logic state transition comprises an XOR logic gate.
Claim 5
Dependent Claim
19 words
A process monitor circuit as in claim 1, wherein said first delay path comprises a plurality of OR gates.
Claim 6
Dependent Claim
18 words
A process monitor circuit as in claim 1, wherein said second delay path comprises a plurality of inverters.
Claim 7
Dependent Claim
42 words
A process monitor circuit as in claim 1, wherein said first delay path comprises PMOS and NMOS transistors, and the difference between said first and second delays is substantially caused by a difference in switching times of said PMOS and NMOS transistors.
Claim 8
Dependent Claim
23 words
A process monitor circuit as in claim 4, wherein each of said plurality of OR gates comprises a NOR gate and an inverter.
Claim 9
Independent Claim
229 words
A method for monitoring a process, comprising the steps of: using a first delay path comprising a plurality of logic gates having an input terminal and a first logic output terminal, said first delay path providing after a first delay a first logic transition at said first output terminal, when a first input logic state transition signal is received at said input terminal, and providing after a second delay a second logic state transition signal at said first output terminal, when a second logic state transition opposite said first input logic state transition is received at said input terminal, said first and second delays being distinguishably different; using a second delay path having a second output terminal and connected to said input terminal, said second delay path providing after a third delay a third logic state transition output signal at said second output terminal, when said first input logic state transition is received at said input terminal, and providing after a fourth delay a fourth logic state transition at said second output terminal, when said second input logic state transition is received at said input terminal, said third and fourth delays being substantially equal; and using means, having a third output terminal connected to said first and second output terminals, for providing a logic state transition upon receiving each of said first, second, third and fourth logic state transitions.
Claim 10
Independent Claim
229 words
A method for monitoring a process, comprising the steps of: using a first delay path comprising a plurality of logic gates having an input terminal and a first logic output terminal, said first delay path providing after a first delay a first logic transition at said first output terminal, when a first input logic state transition signal is received at said input terminal, and providing after a second delay a second logic state transition signal at said first output terminal, when a second logic state transition opposite said first input logic state transition is received at said input terminal, said first and second delays being distinguishably different; using a second delay path having a second output terminal and connected to said input terminal, said second delay path providing after a third delay a third logic state transition output signal at said second output terminal, when said first input logic state transition is received at said input terminal, and providing after a fourth delay a fourth logic state transition at said second output terminal, when said second input logic state transition is received at said input terminal, said third and fourth delays being substantially equal; and using means, having a third output terminal connected to said first and second output terminals, for providing a logic state transition upon receiving each of said first, second, third and fourth logic state transitions.
Claim 11
Dependent Claim
24 words
A method for monitoring a process as in claim 8, wherein said means for providing a logic state transition comprises an XNOR logic gate.
Claim 12
Dependent Claim
24 words
A method for monitoring a process as in claim 8, wherein said means for providing a logic state transition comprises an XOR logic gate.
Claim 13
Dependent Claim
21 words
A method for monitoring a process as in claim 8, wherein said first delay path comprises a plurality of OR gates.
Claim 14
Dependent Claim
20 words
A method for monitoring a process as in claim 8, wherein said second delay path comprises a plurality of inverters.
Claim 15
Dependent Claim
44 words
A method for monitoring a process as in claim 8, wherein said first delay means comprises PMOS and NMOS transistors, and said difference between said first and second delays is caused substantially by the difference in switching times of said PMOS and NMOS transistors.
Claim 16
Dependent Claim
25 words
A method for monitoring a process as in claim 11, wherein each of said plurality of OR gates comprises a NOR gate and an inverter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |