US6063681A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicide formation using two metalizations
Assignee: SK Hynix Inc
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Filing: 1998-07-20
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Granted: 2000-05-16
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Expires: 2018-07-20
Abstract
Abstract Semiconductor device and method for fabricating the same, is disclosed, in which LDD regions and source/drain regions are provided with a silicide for reducing resistances to prevent short channel, the device including a gate insulating film and a gate electrode formed stacked on a prescribed region of a semiconductor substrate, sidewall spacers formed at both sides of the gate insulating film and the gate electrode, first impurity regions formed in surfaces of the semiconductor substrate under the sidewall spacers, second impurity regions formed in the semiconductor substrate on both sides of the sidewall spacers and the first impurity regions, first silicide films at surfaces of the first impurity regions, and second silicide films at surfaces of the gate electrode and the second impurity regions.
Inventors
- 👤 Jeong Hwan Son
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0213; H10P; H10P10/00; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/021; H10D64/015
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
168 words
A method for fabricating a semiconductor device, comprising the steps of: forming a stack of gate insulting film and a gate electrode over a semiconductor substrate; forming first sidewall spacers at both sides of the stack of the gate insulating film and the gate electrode; forming first impurity regions using the first sidewall spacers as masks; depositing a first metal layer on an entire surface; annealing the first metal layer, to form first silicide films in surfaces of the first impurity regions and the gate electrode; removing the first metal layer which made no reaction; forming second sidewall spacers at sides of the first sidewall spacers at sides of the stack of the gate insulting film and the gate electrode; forming source/drain regions in the semiconductor substrate using the second sidewall spacers as masks; depositing a second metal layer on an entire surface; conducting annealing to form second silicide films on the gate electrode and the source/drain regions; and, removing the second metal layer which made no reaction.
Claim 2
Independent Claim
168 words
A method for fabricating a semiconductor device, comprising the steps of: forming a stack of gate insulting film and a gate electrode over a semiconductor substrate; forming first sidewall spacers at both sides of the stack of the gate insulating film and the gate electrode; forming first impurity regions using the first sidewall spacers as masks; depositing a first metal layer on an entire surface; annealing the first metal layer, to form first silicide films in surfaces of the first impurity regions and the gate electrode; removing the first metal layer which made no reaction; forming second sidewall spacers at sides of the first sidewall spacers at sides of the stack of the gate insulting film and the gate electrode; forming source/drain regions in the semiconductor substrate using the second sidewall spacers as masks; depositing a second metal layer on an entire surface; conducting annealing to form second silicide films on the gate electrode and the source/drain regions; and, removing the second metal layer which made no reaction.
Claim 3
Dependent Claim
21 words
A method as claimed in claim 1, wherein the first, and second metal layers are formed of titanium, nickel, or cobalt.
Claim 4
Dependent Claim
22 words
A method as claimed in claim 1, wherein the first, and second metal layers are formed of metals different from each other.
Claim 5
Dependent Claim
20 words
A method as claimed in claim 1, wherein the first silicide film is formed thinner than the second silicide film.
Claim 6
Independent Claim
174 words
A method for fabricating a semiconductor device, comprising the steps of: forming a stack of gate insulting film and a gate electrode over a semiconductor substrate; forming first sidewall spacers at both sides of the stack of the gate insulating film and the gate electrode; forming first impurity regions using the first sidewall spacers as masks; depositing a first metal layer on an entire surface; forming second sidewall spacers on the first metal layer on the first sidewall spacers; forming second impurity regions in the semiconductor substrate on both sides of the gate electrode and the second sidewall spacers; forming a second metal layer on an entire surface of the semiconductor substrate; conducting annealing to form first silicide films in the first impurity regions under the second sidewall spacers and to form second silicide films in surfaces of the gate electrode and the second impurity regions; removing exposed second metal layer which made no reaction; removing the second sidewall spacers; and, removing the first metal layer remained at sides of the first sidewall spacers.
Claim 7
Independent Claim
174 words
A method for fabricating a semiconductor device, comprising the steps of: forming a stack of gate insulting film and a gate electrode over a semiconductor substrate; forming first sidewall spacers at both sides of the stack of the gate insulating film and the gate electrode; forming first impurity regions using the first sidewall spacers as masks; depositing a first metal layer on an entire surface; forming second sidewall spacers on the first metal layer on the first sidewall spacers; forming second impurity regions in the semiconductor substrate on both sides of the gate electrode and the second sidewall spacers; forming a second metal layer on an entire surface of the semiconductor substrate; conducting annealing to form first silicide films in the first impurity regions under the second sidewall spacers and to form second silicide films in surfaces of the gate electrode and the second impurity regions; removing exposed second metal layer which made no reaction; removing the second sidewall spacers; and, removing the first metal layer remained at sides of the first sidewall spacers.
Claim 8
Dependent Claim
21 words
A method as claimed in claim 5, wherein the first, and second metal layers are formed of titanium, nickel, or cobalt.
Claim 9
Dependent Claim
22 words
A method as claimed in claim 5, wherein the first, and second metal layers are formed of metals different from each other.
Claim 10
Dependent Claim
20 words
A method as claimed in claim 5, wherein the first silicide film is formed thinner than the second silicide film.
Claim 11
Dependent Claim
21 words
A method as claimed in claim 5, wherein the second sidewall spacers are formed at a temperature lower than 600° C.
Claim 12
Independent Claim
185 words
A method for fabricating a semiconductor device, comprising the steps of: forming a stack of gate insulting film and a gate electrode over a semiconductor substrate; forming first sidewall spacers at both sides of the stack of the gate insulating film and the gate electrode; depositing a first metal layer on an entire surface; forming doped second sidewall spacers on the first metal layer on the first sidewall spacers; forming first impurity regions in the semiconductor substrate on both sides of the gate electrode and the second sidewall spacers; forming a second metal layer on an entire surface of the semiconductor substrate; conducting annealing to form first silicide films at surfaces of the semiconductor substrate under the second sidewall spacers and to form second silicide films in surfaces of the gate electrode and the first impurity regions; forming second impurity regions bounding the first silicide films from below by means of annealing conducted for activating the first impurity regions; removing exposed second metal layer which made no reaction; removing the second sidewall spacers; and, removing the first metal layer remained on the first sidewall spacers.
Claim 13
Independent Claim
185 words
A method for fabricating a semiconductor device, comprising the steps of: forming a stack of gate insulting film and a gate electrode over a semiconductor substrate; forming first sidewall spacers at both sides of the stack of the gate insulating film and the gate electrode; depositing a first metal layer on an entire surface; forming doped second sidewall spacers on the first metal layer on the first sidewall spacers; forming first impurity regions in the semiconductor substrate on both sides of the gate electrode and the second sidewall spacers; forming a second metal layer on an entire surface of the semiconductor substrate; conducting annealing to form first silicide films at surfaces of the semiconductor substrate under the second sidewall spacers and to form second silicide films in surfaces of the gate electrode and the first impurity regions; forming second impurity regions bounding the first silicide films from below by means of annealing conducted for activating the first impurity regions; removing exposed second metal layer which made no reaction; removing the second sidewall spacers; and, removing the first metal layer remained on the first sidewall spacers.
Claim 14
Dependent Claim
25 words
A method as claimed in claim 10, wherein the second sidewall spacers are formed of BSG(Boro-Silicate Glass) doped with boron, or polysilicon doped with boron.
Claim 15
Dependent Claim
25 words
A method as claimed in claim 10, wherein the second sidewall spacers are formed of PSG(Phospho-Silicate Glass) doped with phosphorus, or polysilicon doped with phosphorus.
Claim 16
Dependent Claim
21 words
A method as claimed in claim 10, wherein the first, and second metal layers are formed of titanium, nickel, or cobalt.
Claim 17
Dependent Claim
22 words
A method as claimed in claim 10, wherein the first, and second metal layers are formed of metals different from each other.
Claim 18
Dependent Claim
20 words
A method as claimed in claim 10, wherein the second silicide film is formed deeper than the first silicide film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |