Reduced mask CMOS salicided process

Claim 1

A method for manufacturing a CMOS device on a semiconductor substrate, the method comprising: forming a plurality of field oxide regions on said semiconductor substrate; forming a first oxide layer on said plurality of field oxide regions; forming a first silicon nitride layer on said first oxide layer; patterning a first photoresist on said semiconductor substrate to expose a portion of said semiconductor substrate; forming a first conductivity well in said semiconductor substrate by a first ion implantation using said first photoresist as a mask; forming a first liquid phase deposition oxide (LPD-oxide) on said semiconductor substrate over said first conductive well; removing said first photoresist; forming a second conductivity well in said semiconductor substrate by a second ion implantation using said first LPD-oxide as a mask; removing said first LPD-oxide; removing said first silicon nitride layer; removing said first oxide layer; forming a second oxide layer on said semiconductor substrate as a gate oxide; forming an undoped polysilicon layer on said second oxide layer; forming a second silicon nitride layer on said undoped polysilicon layer to act as an anti-reflective coating (ARC); patterning said second silicon nitride layer, said polysilicon layer, and said second oxide layer to form gates on said first, second conductive wells, respectively; patterning a second photoresist on said second conductive well; performing a third ion implantation using said second photoresist as a mask to dope second conductive type ions into said first conductive well, thereby forming second conductive type doped regions; forming a second LPD-oxide layer on said first conductive well and along a surface of said gate on said first conductive well; performing a first thermal anneal to condense said second LPD-oxide layer, a silicon oxynitride layer being simultaneously formed on said second conductive well and along a surface of said gate on said second conductive well; forming oxide side wall spacers having first conductive type ions on side walls of said gates; forming a self-aligned silicide (SALICIDE) on said semiconductor substrate and a polycide on said gates; patterning a third photoresist on said first well; performing a forth ion implantation using said third photoresist as a mask to dope first conductive type ions into said second conductive well; removing said third photoresist; patterning a forth photoresist on said second well; performing a fifth ion implantation using said forth photoresist as a mask to dope second conductive type ions into said first conductive well; removing said forth photoresist; and performing a second thermal anneal to form source and drain junction adjacent to said gates, and extended source and drain under said oxide side wall spacers.

Claim 2

A method for manufacturing a CMOS device on a semiconductor substrate, the method comprising: forming a plurality of field oxide regions on said semiconductor substrate; forming a first oxide layer on said plurality of field oxide regions; forming a first silicon nitride layer on said first oxide layer; patterning a first photoresist on said semiconductor substrate to expose a portion of said semiconductor substrate; forming a first conductivity well in said semiconductor substrate by a first ion implantation using said first photoresist as a mask; forming a first liquid phase deposition oxide (LPD-oxide) on said semiconductor substrate over said first conductive well; removing said first photoresist; forming a second conductivity well in said semiconductor substrate by a second ion implantation using said first LPD-oxide as a mask; removing said first LPD-oxide; removing said first silicon nitride layer; removing said first oxide layer; forming a second oxide layer on said semiconductor substrate as a gate oxide; forming an undoped polysilicon layer on said second oxide layer; forming a second silicon nitride layer on said undoped polysilicon layer to act as an anti-reflective coating (ARC); patterning said second silicon nitride layer, said polysilicon layer, and said second oxide layer to form gates on said first, second conductive wells, respectively; patterning a second photoresist on said second conductive well; performing a third ion implantation using said second photoresist as a mask to dope second conductive type ions into said first conductive well, thereby forming second conductive type doped regions; forming a second LPD-oxide layer on said first conductive well and along a surface of said gate on said first conductive well; performing a first thermal anneal to condense said second LPD-oxide layer, a silicon oxynitride layer being simultaneously formed on said second conductive well and along a surface of said gate on said second conductive well; forming oxide side wall spacers having first conductive type ions on side walls of said gates; forming a self-aligned silicide (SALICIDE) on said semiconductor substrate and a polycide on said gates; patterning a third photoresist on said first well; performing a forth ion implantation using said third photoresist as a mask to dope first conductive type ions into said second conductive well; removing said third photoresist; patterning a forth photoresist on said second well; performing a fifth ion implantation using said forth photoresist as a mask to dope second conductive type ions into said first conductive well; removing said forth photoresist; and performing a second thermal anneal to form source and drain junction adjacent to said gates, and extended source and drain under said oxide side wall spacers.