CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process

Claim 1

A method for fabricating a CMOS device, on a semiconductor substrate, comprising the steps of: forming field oxide regions in said semiconductor substrate; ion implanting a first conductivity imparting dopant into an area of said semiconductor substrate, to form an N well region, in an area of said semiconductor substrate that is used for a PFET region, of said CMOS device; ion implanting a second conductivity imparting dopant into said PFET region, to adjust the threshold voltage of devices fabricated in said PFET region; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate that is used for an NFET region, of said CMOS device, to form a channel stop and a P well region; ion implanting a fourth conductivity imparting dopant into an area of said semiconductor substrate that is used for said NFET region of said CMOS device, to adjust the threshold voltage of devices fabricated in said NFET region; growing a gate insulator layer on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer and on said field oxide regions; anisotropic etching of said polysilicon layer to form polysilicon gate structures on said gate insulator layer; depositing a first sidewall insulator layer on said polysilicon gate structures, and on said gate insulator layer and field oxide regions, not covered by said polysilicon gate structures; depositing a second sidewall insulator layer on said first sidewall insulator layer, forming a dual sidewall insulator layer; anisotropic etching of said dual sidewall insulator layer to form a dual insulator spacer on sides of said polysilicon gate structures; ion implanting a fifth conductivity imparting dopant into said NFET region, of said CMOS device, not covered by said polysilicon gate structure, and not covered by said dual insulator spacer to form N type, heavily doped source and drain regions; ion implanting a sixth conductivity imparting dopant into said PFET region, of said CMOS device, not covered by said polysilicon gate structure, and not covered by said dual insulator spacer, to form P type, heavily doped source and drain regions; first rapid thermal annealing to activate the dopants in said N type, heavily doped source and drain regions, and in said P type, heavily doped source and drain regions; precleaning said NFET region, and said PFET region, using a dilute hydrofluoric acid solution; depositing a metal layer thereon after said precleaning; second rapid thermal annealing to convert said metal layer to a metal silicide layer, on the top surface of said polysilicon gate structures, on the top surface of said N type, heavily doped source and drain regions, and on the top surface of said P type, heavily doped source and drain regions, while leaving unreacted metal on the top surface of said dual insulator layer, and on the top surface of said field oxide region; removing said unreacted metal from the top surface of said dual insulator layer, and from the top surface of said field oxide region; removing of said second sidewall insulator layer, from said dual insulator layer, exposing a peripheral channel region, covered with said first insulator sidewall layer, with said peripheral channel region located between said polysilicon gate structures and said metal silicide, on said N type, heavily doped source and drain regions, for said NFET region, and located between said polysilicon gate structures and metal silicide, on said P type, heavily doped source and drain regions, for said PFET regions; ion implanting a seventh conductivity imparting dopant into said peripheral channel region, in said NFET region, to create a P type, pocket ion implanted region; ion implanting an eight conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra lightly doped source and drain region; ion implanting a ninth conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra shallow junction extension; ion implanting a tenth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a N type, pocket ion implanted region; ion implanting an eleventh conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra lightly doped source and drain region; ion implanting a twelfth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra shallow junction extension; third rapid thermal annealing, to activate the dopants in said P type, ultra shallow junction extension regions, and in said N type, ultra shallow junction extension regions; depositing an interlevel insulator layer thereon after third annealing; opening contact holes in said interlevel insulator layer to metal silicide layers on said N type, heavily doped source and drain regions, to said metal silicide layers on said P type, heavily doped source and drain regions, and to said metal silicide layers on said polysilicon gate structures; depositing a interconnect metallization layer after forming said contact; and patterning of said interconnect metallization layer to form metal contact structures to said N type, heavily doped source and drain regions, to said P type, heavily doped source and drain regions, and to said polysilicon gate structures.

Claim 2

A method for fabricating a CMOS device, on a semiconductor substrate, comprising the steps of: forming field oxide regions in said semiconductor substrate; ion implanting a first conductivity imparting dopant into an area of said semiconductor substrate, to form an N well region, in an area of said semiconductor substrate that is used for a PFET region, of said CMOS device; ion implanting a second conductivity imparting dopant into said PFET region, to adjust the threshold voltage of devices fabricated in said PFET region; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate that is used for an NFET region, of said CMOS device, to form a channel stop and a P well region; ion implanting a fourth conductivity imparting dopant into an area of said semiconductor substrate that is used for said NFET region of said CMOS device, to adjust the threshold voltage of devices fabricated in said NFET region; growing a gate insulator layer on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer and on said field oxide regions; anisotropic etching of said polysilicon layer to form polysilicon gate structures on said gate insulator layer; depositing a first sidewall insulator layer on said polysilicon gate structures, and on said gate insulator layer and field oxide regions, not covered by said polysilicon gate structures; depositing a second sidewall insulator layer on said first sidewall insulator layer, forming a dual sidewall insulator layer; anisotropic etching of said dual sidewall insulator layer to form a dual insulator spacer on sides of said polysilicon gate structures; ion implanting a fifth conductivity imparting dopant into said NFET region, of said CMOS device, not covered by said polysilicon gate structure, and not covered by said dual insulator spacer to form N type, heavily doped source and drain regions; ion implanting a sixth conductivity imparting dopant into said PFET region, of said CMOS device, not covered by said polysilicon gate structure, and not covered by said dual insulator spacer, to form P type, heavily doped source and drain regions; first rapid thermal annealing to activate the dopants in said N type, heavily doped source and drain regions, and in said P type, heavily doped source and drain regions; precleaning said NFET region, and said PFET region, using a dilute hydrofluoric acid solution; depositing a metal layer thereon after said precleaning; second rapid thermal annealing to convert said metal layer to a metal silicide layer, on the top surface of said polysilicon gate structures, on the top surface of said N type, heavily doped source and drain regions, and on the top surface of said P type, heavily doped source and drain regions, while leaving unreacted metal on the top surface of said dual insulator layer, and on the top surface of said field oxide region; removing said unreacted metal from the top surface of said dual insulator layer, and from the top surface of said field oxide region; removing of said second sidewall insulator layer, from said dual insulator layer, exposing a peripheral channel region, covered with said first insulator sidewall layer, with said peripheral channel region located between said polysilicon gate structures and said metal silicide, on said N type, heavily doped source and drain regions, for said NFET region, and located between said polysilicon gate structures and metal silicide, on said P type, heavily doped source and drain regions, for said PFET regions; ion implanting a seventh conductivity imparting dopant into said peripheral channel region, in said NFET region, to create a P type, pocket ion implanted region; ion implanting an eight conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra lightly doped source and drain region; ion implanting a ninth conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra shallow junction extension; ion implanting a tenth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a N type, pocket ion implanted region; ion implanting an eleventh conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra lightly doped source and drain region; ion implanting a twelfth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra shallow junction extension; third rapid thermal annealing, to activate the dopants in said P type, ultra shallow junction extension regions, and in said N type, ultra shallow junction extension regions; depositing an interlevel insulator layer thereon after third annealing; opening contact holes in said interlevel insulator layer to metal silicide layers on said N type, heavily doped source and drain regions, to said metal silicide layers on said P type, heavily doped source and drain regions, and to said metal silicide layers on said polysilicon gate structures; depositing a interconnect metallization layer after forming said contact; and patterning of said interconnect metallization layer to form metal contact structures to said N type, heavily doped source and drain regions, to said P type, heavily doped source and drain regions, and to said polysilicon gate structures.

Claim 19

A method for fabricating a CMOS device, on a semiconductor substrate, incorporating a pocket ion implanted region and a ultra shallow junction extension, in a peripheral channel region, created via use of a dual insulator spacer, comprising the steps of: forming field oxide regions in said semiconductor substrate; ion implanting a first conductivity imparting dopant into said semiconductor substrate, to form an N well region in an area of said semiconductor substrate used for a PFET region of said CMOS device; ion implanting a second conductivity imparting dopant into said PFET region, to adjust the threshold voltage of devices fabricated in said PFET region; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate that is used for an NFET region of said CMOS device, to form a channel stop region and a P well region; ion implanting a fourth conductivity imparting dopant into said semiconductor substrate, in an region of said semiconductor substrate to be used said NFET region of said CMOS device, to adjust the threshold voltage of devices fabricated in said NFET region; growing a gate insulator layer on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer, and on said field oxide regions; anisotropic etching of said polysilicon layer to form narrow polysilicon gate structures on said gate insulator layer; depositing a first silicon oxide layer on said narrow polysilicon gate structures, and on said gate insulator layer, and on said field oxide regions, not covered by said narrow polysilicon gate structures; depositing a titanium nitride layer on said first silicon oxide layer, forming a dual sidewall insulator layer of an overlying said titanium nitride layer and an underlying said first silicon oxide layer; anisotropic etching of said dual sidewall insulator layer to form said dual insulator spacer, on the sides of said narrow polysilicon gate structure; ion implanting a fifth conductivity imparting dopant into said NFET region of said CMOS device, not covered by said narrow polysilicon gate structure, and not covered by said dual insulator spacer, to form N type, heavily doped source and drain regions; ion implanting a sixth conductivity imparting dopant into PFET region of said CMOS device, not covered by said narrow polysilicon gate structure, and not covered by said dual insulator spacer, to form P type, heavily doped source and drain regions; first rapid thermal annealing to activate dopants in said N type, heavily doped source and drain regions, and to activate dopants in said P type, heavily doped source and drain regions; precleaning said NFET region and said PFET region using a dilute hydrofluoric acid solution; depositing a titanium layer thereon after said precleaning; second rapid thermal annealing to convert said titanium layer to a titanium silicide layer on the top surface of said narrow polysilicon gate structure, on top surface of said N type, heavily doped regions, and on top surface of said P type, heavily doped regions, while leaving unreacted titanium on the top surface of said titanium nitride layer, and on the top surface of said field oxide regions; removing of said unreacted titanium from the top surface of said titanium nitride layer, and from the top surface of said field oxide regions; removing of said titanium nitride layer from said dual insulator spacer, exposing said peripheral channel region, covered with said first silicon oxide layer, with said peripheral channel region located between said narrow polysilicon gate structure and said titanium silicide layers, on said N type, heavily doped source and drain regions, in said NFET region of said CMOS device, and located between said narrow polysilicon gate structure and said titanium silicide layers, on said P type, heavily doped source and drain regions, in said PFET region of said CMOS device; ion implanting a seventh conductivity imparting dopant into said peripheral channel region, in said NFET region, to create a P type, pocket ion implanted region; ion implanting an eight conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra lightly doped source and drain region; ion implanting a ninth conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra shallow junction extension; ion implanting a tenth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create an N type, pocket ion implanted region; ion implanting an eleventh conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra lightly doped source and drain region; ion implanting a twelfth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra shallow junction extension; third rapid thermal annealing to activate dopants in said ultra shallow junction extension regions; depositing an interlevel insulator layer thereon after third annealing; opening contact holes in said interlevel insulator layer to said titanium silicide on said N type, heavily doped source and drain regions, to said titanium silicide on said P type, heavily doped source and drain regions, and to titanium silicide on said narrow polysilicon gate structures; depositing an interconnect metallization layer thereon after forming said contact holes; and patterning of said interconnect metallization layer to form metal contacts to said N type, heavily doped source and drain regions, to said P type, heavily doped source and drain regions, and to said narrow polysilicon gate structures.

Claim 20

A method for fabricating a CMOS device, on a semiconductor substrate, incorporating a pocket ion implanted region and a ultra shallow junction extension, in a peripheral channel region, created via use of a dual insulator spacer, comprising the steps of: forming field oxide regions in said semiconductor substrate; ion implanting a first conductivity imparting dopant into said semiconductor substrate, to form an N well region in an area of said semiconductor substrate used for a PFET region of said CMOS device; ion implanting a second conductivity imparting dopant into said PFET region, to adjust the threshold voltage of devices fabricated in said PFET region; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate that is used for an NFET region of said CMOS device, to form a channel stop region and a P well region; ion implanting a fourth conductivity imparting dopant into said semiconductor substrate, in an region of said semiconductor substrate to be used said NFET region of said CMOS device, to adjust the threshold voltage of devices fabricated in said NFET region; growing a gate insulator layer on said semiconductor substrate; depositing a polysilicon layer on said gate insulator layer, and on said field oxide regions; anisotropic etching of said polysilicon layer to form narrow polysilicon gate structures on said gate insulator layer; depositing a first silicon oxide layer on said narrow polysilicon gate structures, and on said gate insulator layer, and on said field oxide regions, not covered by said narrow polysilicon gate structures; depositing a titanium nitride layer on said first silicon oxide layer, forming a dual sidewall insulator layer of an overlying said titanium nitride layer and an underlying said first silicon oxide layer; anisotropic etching of said dual sidewall insulator layer to form said dual insulator spacer, on the sides of said narrow polysilicon gate structure; ion implanting a fifth conductivity imparting dopant into said NFET region of said CMOS device, not covered by said narrow polysilicon gate structure, and not covered by said dual insulator spacer, to form N type, heavily doped source and drain regions; ion implanting a sixth conductivity imparting dopant into PFET region of said CMOS device, not covered by said narrow polysilicon gate structure, and not covered by said dual insulator spacer, to form P type, heavily doped source and drain regions; first rapid thermal annealing to activate dopants in said N type, heavily doped source and drain regions, and to activate dopants in said P type, heavily doped source and drain regions; precleaning said NFET region and said PFET region using a dilute hydrofluoric acid solution; depositing a titanium layer thereon after said precleaning; second rapid thermal annealing to convert said titanium layer to a titanium silicide layer on the top surface of said narrow polysilicon gate structure, on top surface of said N type, heavily doped regions, and on top surface of said P type, heavily doped regions, while leaving unreacted titanium on the top surface of said titanium nitride layer, and on the top surface of said field oxide regions; removing of said unreacted titanium from the top surface of said titanium nitride layer, and from the top surface of said field oxide regions; removing of said titanium nitride layer from said dual insulator spacer, exposing said peripheral channel region, covered with said first silicon oxide layer, with said peripheral channel region located between said narrow polysilicon gate structure and said titanium silicide layers, on said N type, heavily doped source and drain regions, in said NFET region of said CMOS device, and located between said narrow polysilicon gate structure and said titanium silicide layers, on said P type, heavily doped source and drain regions, in said PFET region of said CMOS device; ion implanting a seventh conductivity imparting dopant into said peripheral channel region, in said NFET region, to create a P type, pocket ion implanted region; ion implanting an eight conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra lightly doped source and drain region; ion implanting a ninth conductivity imparting dopant into said peripheral channel region, in said NFET region, to create an N type, ultra shallow junction extension; ion implanting a tenth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create an N type, pocket ion implanted region; ion implanting an eleventh conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra lightly doped source and drain region; ion implanting a twelfth conductivity imparting dopant into said peripheral channel region, in said PFET region, to create a P type, ultra shallow junction extension; third rapid thermal annealing to activate dopants in said ultra shallow junction extension regions; depositing an interlevel insulator layer thereon after third annealing; opening contact holes in said interlevel insulator layer to said titanium silicide on said N type, heavily doped source and drain regions, to said titanium silicide on said P type, heavily doped source and drain regions, and to titanium silicide on said narrow polysilicon gate structures; depositing an interconnect metallization layer thereon after forming said contact holes; and patterning of said interconnect metallization layer to form metal contacts to said N type, heavily doped source and drain regions, to said P type, heavily doped source and drain regions, and to said narrow polysilicon gate structures.