US5512502A
Expired / Lapsed
US
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Manufacturing method for semiconductor integrated circuit device
Assignee: Renesas Electronics Corp
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Filing: 1995-03-01
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Granted: 1996-04-30
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Expires: 2015-03-01
Abstract
Abstract In forming a MISFET having a salicide structure, a polysilicon film forming a gate electrode in the MISFET is constructed of a first silicon film having a high n-type impurity concentration on the side of a gate insulating film and a second silicon film having a low n-type impurity concentration on the surface side of the gate electrode. Further, a Ti film is deposited on the second silicon film. The Ti film and the second silicon film are annealed twice at proper different temperatures to thereby promote a silicide reaction and form a low-resistance silicide layer in the second silicon film.
Inventors
- 👤 Fumio Ootsuka
- 👤 Yusuke Nonaka
- 👤 Atsumi Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:50
CPC Classifications
H; H10; H10W; H10W10/00; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10W10/01; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
298 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed on said first silicon layer, said first silicon layer having an impurity concentration of n-type conductivity higher than that of said second silicon layer; (b) patterning said first silicon layer and said second silicon layer to form a gate electrode pattern in a MISFET; (c) depositing a first insulating film over said main surface after said step (b); (d) etching said first insulating film to form a side wall spacer on a side wall of said gate electrode pattern; (e) depositing a high-melting point metal film over said main surface, said gate electrode pattern, and said side wall spacer after said step (d); (f) performing first annealing to cause a silicide reaction between said second silicon layer having a shape of said gate electrode pattern and said high-melting point metal film and thereby form a first silicide layer in said second silicon layer; (g) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacer after said step (f); and (h) performing second annealing at a temperature higher than that of said first annealing after said step (g) to convert said first silicide layer into a second silicide layer having a resistance lower than that of said first silicide layer, said first silicon layer having an impurity concentration of 2×10 20 atoms/cm 3 or more, said second silicon layer having an impurity concentration of 1×10 20 atoms/cm 3 or less, an impurity concentration in an interface between said second silicide layer and said second silicon layer being 1×10 20 atoms/cm 3 or less.
Claim 2
Independent Claim
298 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed on said first silicon layer, said first silicon layer having an impurity concentration of n-type conductivity higher than that of said second silicon layer; (b) patterning said first silicon layer and said second silicon layer to form a gate electrode pattern in a MISFET; (c) depositing a first insulating film over said main surface after said step (b); (d) etching said first insulating film to form a side wall spacer on a side wall of said gate electrode pattern; (e) depositing a high-melting point metal film over said main surface, said gate electrode pattern, and said side wall spacer after said step (d); (f) performing first annealing to cause a silicide reaction between said second silicon layer having a shape of said gate electrode pattern and said high-melting point metal film and thereby form a first silicide layer in said second silicon layer; (g) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacer after said step (f); and (h) performing second annealing at a temperature higher than that of said first annealing after said step (g) to convert said first silicide layer into a second silicide layer having a resistance lower than that of said first silicide layer, said first silicon layer having an impurity concentration of 2×10 20 atoms/cm 3 or more, said second silicon layer having an impurity concentration of 1×10 20 atoms/cm 3 or less, an impurity concentration in an interface between said second silicide layer and said second silicon layer being 1×10 20 atoms/cm 3 or less.
Claim 3
Dependent Claim
66 words
A method according to claim 1, wherein the temperature of said first annealing is in the range of 650° to 700° C.; the temperature of said second annealing is in the range of 800° to 900° C.; said high-melting point metal film is a Ti film; and said second silicon layer has a thickness twice or more of a thickness of said high-melting point metal film.
Claim 4
Dependent Claim
48 words
A method according to claim 2, further comprising the step of: (i) depositing an interlayer insulating film containing phosphorus over said main surface after said step (g); wherein said second annealing is performed after said step (i), and said interlayer insulating film is densified by said second annealing.
Claim 5
Dependent Claim
18 words
A method according to claim 1, wherein said second silicide layer is formed in said second silicon layer.
Claim 6
Independent Claim
273 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed on said first silicon layer, said first silicon layer having an impurity concentration higher than that of said second silicon layer; (b) patterning said first silicon layer and said second silicon layer to form a gate electrode pattern in a MISFET; (c) depositing a first insulating film over said main surface after said step (b); (d) etching said first insulating film to form a side wall spacer on a side wall of said gate electrode pattern; (e) depositing a high-melting point metal (A) film over said main surface, said gate electrode pattern, and said side wall spacer after said step (d); (f) performing first annealing to cause a silicide reaction between said second silicon layer having a shape of said gate electrode pattern and said high-melting point metal film and thereby form a first silicide layer (ASi x ; x<2) in said second silicon layer; (g) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacer after said step (f); and (h) performing second annealing at a temperature higher than that of said first annealing after said step (g) to convert said first silicide layer into a second silicide layer (ASi 2 ) having a resistance lower than that of said first silicide layer, an impurity concentration in an interface between said second silicide layer and said second silicon layer being 1×10 20 atoms/cm 3 or less.
Claim 7
Independent Claim
273 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed on said first silicon layer, said first silicon layer having an impurity concentration higher than that of said second silicon layer; (b) patterning said first silicon layer and said second silicon layer to form a gate electrode pattern in a MISFET; (c) depositing a first insulating film over said main surface after said step (b); (d) etching said first insulating film to form a side wall spacer on a side wall of said gate electrode pattern; (e) depositing a high-melting point metal (A) film over said main surface, said gate electrode pattern, and said side wall spacer after said step (d); (f) performing first annealing to cause a silicide reaction between said second silicon layer having a shape of said gate electrode pattern and said high-melting point metal film and thereby form a first silicide layer (ASi x ; x<2) in said second silicon layer; (g) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacer after said step (f); and (h) performing second annealing at a temperature higher than that of said first annealing after said step (g) to convert said first silicide layer into a second silicide layer (ASi 2 ) having a resistance lower than that of said first silicide layer, an impurity concentration in an interface between said second silicide layer and said second silicon layer being 1×10 20 atoms/cm 3 or less.
Claim 8
Dependent Claim
51 words
A method according to claim 5, wherein said first silicon layer has an n-type impurity concentration of 2×0 20 atoms/cm 3 or more; said second silicon layer has an n-type impurity concentration of 1×10 20 atoms/cm 3 or less; and said second silicide layer is formed in said second silicon layer.
Claim 9
Dependent Claim
26 words
A method according to claim 6, wherein said second silicon layer has a thickness twice or more of a thickness of said high-melting point metal film.
Claim 10
Dependent Claim
16 words
A method according to claim 6, wherein said high-melting point metal film is a Ti film.
Claim 11
Dependent Claim
22 words
A method according to claim 6, wherein the temperature of said first annealing is in the range of 850° to 700° C.
Claim 12
Dependent Claim
22 words
A method according to claim 6, wherein the temperature of said second annealing is in the range of 850° to 900° C.
Claim 13
Dependent Claim
35 words
A method of according to claim 10, further comprising the steps of: (i) depositing an interlayer insulating film containing phosphorus over said main surface after said step (h); and (j) densifying said interlayer insulating film.
Claim 14
Dependent Claim
25 words
A method according to claim 10, wherein said gate electrode pattern having said second silicide layer has a sheet resistance of 10 Ω/sq. or less.
Claim 15
Dependent Claim
53 words
A method according to claim 6, further comprising the step of: (i) depositing an interlayer insulating film containing phosphorus over said main surface after said step (g); wherein said interlayer insulating film is densified by said second annealing, and simultaneously said first silicide layer is reduced in its resistance by said second annealing.
Claim 16
Dependent Claim
22 words
A method according to claim 5, wherein said second silicon layer has an impurity concentration of 1×10 20 atoms/cm 3 or less.
Claim 17
Dependent Claim
26 words
A method according to claim 14, wherein said second silicon layer has a thickness twice or more of a thickness of said high-melting point metal film.
Claim 18
Dependent Claim
26 words
A method according to claim 5, wherein said second silicon layer has a thickness twice or more of a thickness of said high-melting point metal film.
Claim 19
Dependent Claim
30 words
A method according to claim 5, wherein said high-melting point metal film is made of a metal selected from a group consisting of Ti, Pt, Co, Mo, W and Ta.
Claim 20
Independent Claim
246 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a first semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed over said first silicon layer, said second silicon layer having an impurity concentration lower than that of said first silicon layer, a gate electrode pattern of a MISFET being constituted by said first and second silicon layers; (b) forming side wall spacers on side surfaces of said first and second silicon layers, said side wall spacers being made of an insulating material; (c) forming a high-melting point metal film over said main surface, said second silicon layer and said side wall spacers; (d) performing a first annealing to cause a silicide reaction between said second silicon layer and said high-melting point metal film and thereby form a first silicide layer within said second silicon layer such that said first silicide layer does not reach said first silicon layer, said second silicon layer having an impurity concentration of 1×10 20 atoms/cm 3 or less; (e) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacers after step (d); and (f) performing a second annealing at a temperature higher than that of said first annealing after said step (e) to convert said first silicide layer to a second silicide layer having a resistance lower than that of said first silicide layer.
Claim 21
Independent Claim
246 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a first semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed over said first silicon layer, said second silicon layer having an impurity concentration lower than that of said first silicon layer, a gate electrode pattern of a MISFET being constituted by said first and second silicon layers; (b) forming side wall spacers on side surfaces of said first and second silicon layers, said side wall spacers being made of an insulating material; (c) forming a high-melting point metal film over said main surface, said second silicon layer and said side wall spacers; (d) performing a first annealing to cause a silicide reaction between said second silicon layer and said high-melting point metal film and thereby form a first silicide layer within said second silicon layer such that said first silicide layer does not reach said first silicon layer, said second silicon layer having an impurity concentration of 1×10 20 atoms/cm 3 or less; (e) removing an unreacted portion of said high-melting point metal film left on said main surface and said side wall spacers after step (d); and (f) performing a second annealing at a temperature higher than that of said first annealing after said step (e) to convert said first silicide layer to a second silicide layer having a resistance lower than that of said first silicide layer.
Claim 22
Dependent Claim
30 words
A method according to claim 18, wherein an impurity concentration in an interface between said second silicide layer and said second silicon layer is 1×10 20 atoms/cm 3 or less.
Claim 23
Dependent Claim
18 words
A method according to claim 19, wherein said second silicide layer is formed within said second silicon layer.
Claim 24
Dependent Claim
39 words
A method according to claim 20, wherein the temperature of said first annealing is in the range of 650° to 800° C., and wherein the temperature of said second annealing is in the range of 850° to 900° C.
Claim 25
Independent Claim
212 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a first semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed over said first silicon layer, said second silicon layer having an impurity concentration lower than that of said first silicon layer, a gate electrode pattern of an MISFET being constituted by said first and second silicon layers; (b) forming a high-melting point metal film over said main surface and said second silicon layer; (c) performing a first annealing to cause a silicide reaction between said second silicon layer and said high-melting point metal film and thereby form a first silicide layer within said second silicon layer such that said first silicide layer does not reach said first silicon layer, said second silicon layer having an impurity concentration of 1×10 20 atoms/cm 3 or less; (d) removing an unreacted portion of said high-melting point metal film left on said main surface after step (c); and (e) performing a second annealing at a temperature higher than that of said first annealing after said step (d) to convert said first silicide layer to a second silicide layer having a resistance lower than that of said first silicide layer.
Claim 26
Independent Claim
212 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a first semiconductor substrate with both a first silicon layer formed over a main surface of said substrate and a second silicon layer formed over said first silicon layer, said second silicon layer having an impurity concentration lower than that of said first silicon layer, a gate electrode pattern of an MISFET being constituted by said first and second silicon layers; (b) forming a high-melting point metal film over said main surface and said second silicon layer; (c) performing a first annealing to cause a silicide reaction between said second silicon layer and said high-melting point metal film and thereby form a first silicide layer within said second silicon layer such that said first silicide layer does not reach said first silicon layer, said second silicon layer having an impurity concentration of 1×10 20 atoms/cm 3 or less; (d) removing an unreacted portion of said high-melting point metal film left on said main surface after step (c); and (e) performing a second annealing at a temperature higher than that of said first annealing after said step (d) to convert said first silicide layer to a second silicide layer having a resistance lower than that of said first silicide layer.
Claim 27
Dependent Claim
35 words
A method of manufacturing a semiconductor device according to claim 22, wherein an impurity concentration in an interface between said second silicide layer and said second silicon layer is 1×10 20 atoms/cm 3 or less.
Claim 28
Dependent Claim
23 words
A method of manufacturing a semiconductor device according to claim 23, wherein said second silicide layer is formed within said second silicon layer.
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