Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step

Claim 2

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer; c) forming a layer of first insulation material over said polysilicon gate electrode layer; d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) forming thin sidewall spacers of a second insulation material different from said first insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; f) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; g) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said exposed portions of said silicon substrate to form metal silicide over said gate electrode and metal silicide portions on said silicon substrate; h) forming source/drain regions in said silicon substrate beneath said metal silicide portions formed over said exposed portions of said silicon substrate; i) forming a layer of third insulation material over said structure; j) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; and k) forming over said structure a layer of fourth insulation material different from said third insulation material; whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of a source/drain contact opening through said fourth insulation.

Claim 3

The process of claim 1 wherein said layer of first insulation material is selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG).

Claim 4

The process of claim 1 wherein said layer of first insulation material comprises silicon nitride.

Claim 5

The process of claim 1 wherein the thickness of said layer of first insulation material ranges from about 500 Angstroms to about 2000 Angstroms.

Claim 6

The process of claim 1 wherein said step of forming said thin sidewall spacers of a second insulation material different from said first insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon further comprises depositing on said structure a layer of second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride.

Claim 7

The process of claim 5 wherein said layer of second insulation material comprises the same material as said gate oxide layer.

Claim 8

The process of claim 5 wherein the thickness of said layer of second insulation material ranges from about 100 Angstroms to about 1000 Angstroms.

Claim 9

The process of claim 1 wherein said step of forming said metal silicide over said polysilicon gate electrode and over exposed portions of said silicon substrate further includes the steps of: a) depositing a silicide-forming metal over said structure; b) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and c) selectively removing unreacted metal from said structure.

Claim 10

The process of claim 1 wherein said step of forming said source/drain regions in said substrate further comprise implanting said substrate through said metal silicide portions formed thereon, whereby said metal silicide portions on said silicon substrate are in electrical communication with said source/drain regions thereunder.

Claim 11

The process of claim 1 wherein said step of forming said source/drain regions in said substrate occurs before formation of said metal silicide portions on said silicon substrate whereby said metal silicide portions subsequently formed on said silicon substrate are formed over said source/drain regions and in electrical communication with said source/drain regions thereunder.

Claim 12

The process of claim 1 wherein said layer of third insulation material is selected from the group consisting of undoped silicon oxide and silicon nitride.

Claim 13

The process of claim 1 wherein the thickness of said layer of third insulation material over said source/drain regions is greater than 1/2 of the width of said polysilicon gate electrode.

Claim 14

The process of claim 1 wherein the thickness of said layer of third insulation material over said source/drain regions ranges from about 350 Angstroms to about 4000 Angstroms.

Claim 15

The process of claim 1 wherein said layer of third insulation material comprises silicon nitride.

Claim 16

The process of claim 1 wherein said layer of fourth insulation material is selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG).

Claim 17

The process of claim 1 wherein said layer of third insulation material comprises silicon nitride and said layer of fourth insulation material comprises silicon oxide selected from the group consisting of undoped silicon oxide, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide.

Claim 18

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer; c) forming a layer of first insulation material over said polysilicon gate electrode layer selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) depositing on said structure a layer of second insulation material different from said first insulation material, said second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride, and having a thickness ranging from about 100 Angstroms to about 1000 Angstroms; f) forming thin sidewall spacers of said second insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by selective anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; g) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; h) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said exposed portions of said silicon substrate by the steps of: i) depositing a silicide-forming metal over said structure; ii) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and iii) selectively removing unreacted metal from said structure; to thereby form a metal silicide gate portion and metal silicide portions on said silicon substrate; i) forming source/drain regions in said silicon substrate beneath said metal silicide portions formed over said exposed portions of said silicon substrate by implanting said substrate through said metal silicide portions formed thereon, whereby said metal silicide portions on said silicon substrate become metal silicide source/drain portions; j) forming a layer of third insulation material over said structure selected from the group consisting of undoped silicon oxide and silicon nitride, said layer of third insulating material having a thickness, above said source/drain regions, ranging from about 350 Angstroms to about 4000 Angstroms, and greater than 1/2 the width of said polysilicon gate electrode; k) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; and l) forming over said structure a layer of fourth insulation material different from said third insulation material and selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of a source/drain contact opening through said layer of fourth insulation material.

Claim 19

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer; c) forming a layer of first insulation material over said polysilicon gate electrode layer selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) depositing on said structure a layer of second insulation material different from said first insulation material, said second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride, and having a thickness ranging from about 100 Angstroms to about 1000 Angstroms; f) forming thin sidewall spacers of said second insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by selective anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; g) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; h) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said exposed portions of said silicon substrate by the steps of: i) depositing a silicide-forming metal over said structure; ii) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and iii) selectively removing unreacted metal from said structure; to thereby form a metal silicide gate portion and metal silicide portions on said silicon substrate; i) forming source/drain regions in said silicon substrate beneath said metal silicide portions formed over said exposed portions of said silicon substrate by implanting said substrate through said metal silicide portions formed thereon, whereby said metal silicide portions on said silicon substrate become metal silicide source/drain portions; j) forming a layer of third insulation material over said structure selected from the group consisting of undoped silicon oxide and silicon nitride, said layer of third insulating material having a thickness, above said source/drain regions, ranging from about 350 Angstroms to about 4000 Angstroms, and greater than 1/2 the width of said polysilicon gate electrode; k) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; and l) forming over said structure a layer of fourth insulation material different from said third insulation material and selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of a source/drain contact opening through said layer of fourth insulation material.

Claim 20

The process of claim 17 wherein said layer of fourth insulation material comprises silicon oxide selected from the group consisting of undoped silicon oxide, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide.

Claim 21

The process of claim 17 including the further step of forming a source/drain contact opening in said layer of fourth insulation material.

Claim 22

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer; c) forming a layer of first insulation material over said polysilicon gate electrode layer selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) forming source/drain regions in said silicon substrate adjacent said silicon substrate beneath said gate electrode; f) depositing on said structure a layer of second insulation material different from said first insulation material, said second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride, and having a thickness ranging from about 100 Angstroms to about 1000 Angstroms; g) forming thin sidewall spacers of said second insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by selective anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; h) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; i) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said source/drain region in said silicon substrate by the steps of: i) depositing a silicide-forming metal over said structure; ii) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and iii) selectively removing unreacted metal from said structure; to thereby form metal silicide over said gate electrode and metal silicide over said source/drain regions in said silicon substrate; j) forming a layer of third insulation material over said structure selected from the group consisting of undoped silicon oxide and silicon nitride, said layer of third insulating material having a thickness, above said source/drain regions, ranging from about 350 Angstroms to about 4000 Angstroms, and greater than 1/2 the width of said polysilicon gate electrode; k) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; and l) forming over said structure a layer of fourth insulation material different from said third insulation material and selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of a source/drain contact opening through said layer of fourth insulation material.

Claim 23

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer; c) forming a layer of first insulation material over said polysilicon gate electrode layer selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) forming source/drain regions in said silicon substrate adjacent said silicon substrate beneath said gate electrode; f) depositing on said structure a layer of second insulation material different from said first insulation material, said second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride, and having a thickness ranging from about 100 Angstroms to about 1000 Angstroms; g) forming thin sidewall spacers of said second insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by selective anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; h) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; i) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said source/drain region in said silicon substrate by the steps of: i) depositing a silicide-forming metal over said structure; ii) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and iii) selectively removing unreacted metal from said structure; to thereby form metal silicide over said gate electrode and metal silicide over said source/drain regions in said silicon substrate; j) forming a layer of third insulation material over said structure selected from the group consisting of undoped silicon oxide and silicon nitride, said layer of third insulating material having a thickness, above said source/drain regions, ranging from about 350 Angstroms to about 4000 Angstroms, and greater than 1/2 the width of said polysilicon gate electrode; k) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; and l) forming over said structure a layer of fourth insulation material different from said third insulation material and selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of a source/drain contact opening through said layer of fourth insulation material.

Claim 24

The process of claim 20 wherein said layer of fourth insulation material comprises silicon oxide selected from the group consisting of undoped silicon oxide, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide.

Claim 25

The process of claim 20 including the further step of forming a source/drain contact opening in said layer of fourth insulation material.

Claim 26

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer, said polysilicon layer having a thickness ranging from about 1000 Angstroms to about 3500 Angstroms; c) forming a layer of first insulation material over said polysilicon gate electrode layer selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG), said layer of first insulating material having a thickness ranging from about 500 Angstroms to about 2000 Angstroms; d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) depositing on said structure a layer of second insulation material different from said first insulation material, said second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride, and having a thickness ranging from about 100 Angstroms to about 1000 Angstroms; f) forming thin sidewall spacers of said second insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by selective anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; g) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; h) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said exposed portions of said silicon substrate by the steps of: i) depositing a silicide-forming metal over said structure; ii) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and iii) selectively removing unreacted metal from said structure; to thereby form a metal silicide gate portion and metal silicide portions on said silicon substrate; i) forming source/drain regions in said silicon substrate beneath said metal silicide portions formed over said exposed portions of said silicon substrate by implanting said substrate through said metal silicide portions formed thereon, whereby said metal silicide portions on said silicon substrate become metal silicide source/drain portions; j) forming a layer of third insulation material over said structure selected from the group consisting of undoped silicon oxide and silicon nitride, said layer of third insulating material having a thickness ranging from about 350 Angstroms to about 4000 Angstroms; k) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; l) forming over said structure a layer of fourth insulation material different from said third insulation material selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); and m) forming a source/drain contact opening in said layer of fourth insulation material; whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of said source/drain contact opening through said layer of fourth insulation material.

Claim 27

A process for forming self-aligned contacts to an MOS device on an integrated circuit structure which comprises: a) forming a gate oxide layer on a silicon substrate; b) forming a polysilicon gate electrode layer over said gate oxide layer, said polysilicon layer having a thickness ranging from about 1000 Angstroms to about 3500 Angstroms; c) forming a layer of first insulation material over said polysilicon gate electrode layer selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG), said layer of first insulating material having a thickness ranging from about 500 Angstroms to about 2000 Angstroms; d) patterning said layer of first insulation layer and said polysilicon gate electrode layer to form a polysilicon gate electrode having its upper surface covered with said first insulation material; e) depositing on said structure a layer of second insulation material different from said first insulation material, said second insulation material selected from the group consisting of undoped silicon oxide and silicon nitride, and having a thickness ranging from about 100 Angstroms to about 1000 Angstroms; f) forming thin sidewall spacers of said second insulation material on the sidewalls of said polysilicon gate electrode and said first insulation material thereon by selective anisotropic etching of said second insulation material and of exposed portions of said gate oxide layer to expose portions of said silicon substrate; g) selectively removing said first insulation material over said polysilicon gate electrode to expose the upper surface of said polysilicon gate electrode; h) forming metal silicide simultaneously on said exposed surface of said polysilicon gate electrode and over said exposed portions of said silicon substrate by the steps of: i) depositing a silicide-forming metal over said structure; ii) annealing said structure at a temperature sufficient to cause said silicide-forming metal to react with said polysilicon gate electrode and said exposed portions of said silicon substrate to form said metal silicide; and iii) selectively removing unreacted metal from said structure; to thereby form a metal silicide gate portion and metal silicide portions on said silicon substrate; i) forming source/drain regions in said silicon substrate beneath said metal silicide portions formed over said exposed portions of said silicon substrate by implanting said substrate through said metal silicide portions formed thereon, whereby said metal silicide portions on said silicon substrate become metal silicide source/drain portions; j) forming a layer of third insulation material over said structure selected from the group consisting of undoped silicon oxide and silicon nitride, said layer of third insulating material having a thickness ranging from about 350 Angstroms to about 4000 Angstroms; k) anisotropically etching said layer of third insulation material to form thick sidewall spacers of said third insulation material on said thin sidewall spacers and third insulation material over said metal silicide formed on said gate electrode; l) forming over said structure a layer of fourth insulation material different from said third insulation material selected from the group consisting of undoped silicon oxide, silicon nitride, phosphorus-doped silicon oxide (PSG), boron-doped silicon oxide (BSG), and boron and phosphorus doped silicon oxide (BPSG); and m) forming a source/drain contact opening in said layer of fourth insulation material; whereby said third insulation material over said metal silicide gate electrode portion will protect said metal silicide gate electrode portion from any misalignment during formation of said source/drain contact opening through said layer of fourth insulation material.