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US6038195A
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Synchronous memory device having a delay time register and method of operating same
Assignee: Rambus Inc
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Filing: 1998-11-20
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Granted: 2000-03-14
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Expires: 2018-11-20
Abstract
Abstract The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 9 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:36
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
76 words
A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; a register which stores a value which is representative of a delay time after which the memory device responds to a read request; and a plurality of output drivers to output data after the delay time transpires and synchronously with respect to the external clock signal.
Claim 2
Dependent Claim
76 words
A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; a register which stores a value which is representative of a delay time after which the memory device responds to a read request; and a plurality of output drivers to output data after the delay time transpires and synchronously with respect to the external clock signal.
Claim 3
Dependent Claim
41 words
The memory device of claim 1 further including: clock generation circuitry, coupled to the clock receiver circuitry, to generate at least one internal clock signal; and wherein the plurality of output drivers output data in response to the internal clock signal.
Claim 4
Dependent Claim
25 words
The memory device of claim 1 wherein the plurality of output drivers output data in response to a rising edge of the external clock signal.
Claim 5
Dependent Claim
47 words
The memory device of claim 1 further including: a delay locked loop, coupled to the clock receiver circuitry, to generate an internal clock signal using at least the external clock signal; and wherein the plurality of output drivers output data in response to the internal clock signal.
Claim 6
Dependent Claim
28 words
The memory device of claim 1 wherein the value which is representative of the delay time is stored in the register after power is applied to the device.
Claim 7
Dependent Claim
24 words
The memory device of claim 1 wherein the value stored in the register is representative of one of a plurality of different delay times.
Claim 8
Dependent Claim
22 words
The synchronous memory device of claim 1 wherein the value is representative of a number of clock cycles of the external clock.
Claim 9
Dependent Claim
28 words
The memory device of claim 7 wherein the value which is representative of the delay time is stored in the register after power is applied to the device.
Claim 10
Dependent Claim
47 words
The memory device of claim 8 further including: a delay locked loop, coupled to the clock receiver circuitry, to generate an internal clock signal using at least the external clock signal; and wherein the plurality of output drivers output data in response to the internal clock signal.
Claim 11
Dependent Claim
24 words
The memory device of claim 8 wherein the value stored in the register is representative of one of a plurality of different delay times.
Claim 12
Dependent Claim
72 words
A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; at least one register to store a value which is representative of a delay time; and wherein in response to a read request, the memory device outputs data after the delay time transpires and synchronously with respect to the external clock signal.
Claim 13
Dependent Claim
72 words
A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; at least one register to store a value which is representative of a delay time; and wherein in response to a read request, the memory device outputs data after the delay time transpires and synchronously with respect to the external clock signal.
Claim 14
Dependent Claim
45 words
The memory device of claim 11 further including: clock generation circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal; and an output driver, coupled to the internal clock generation circuitry, to output the data in response to the internal clock signal.
Claim 15
Dependent Claim
23 words
The memory device of claim 12 wherein the output driver outputs data in response to a rising edge of the internal clock signal.
Claim 16
Dependent Claim
45 words
The memory device of claim 11 further including a delay locked loop, coupled to the clock receiver circuitry, to generate an internal clock signal using at least the external clock signal and wherein the output driver outputs data in response to the internal clock signal.
Claim 17
Dependent Claim
26 words
The memory device of claim 11 wherein the memory device, in response to a control register access, stores a value in the at least one register.
Claim 18
Dependent Claim
24 words
The memory device of claim 11 wherein the value stored in the register is representative of one of a plurality of available delay times.
Claim 19
Dependent Claim
23 words
The synchronous memory device of claim 11 wherein the value is representative of a number of clock cycles of the external clock signal.
Claim 20
Dependent Claim
28 words
The memory device of claim 17 wherein the value which is representative of the delay time is stored in the register after power is applied to the device.
Claim 21
Dependent Claim
47 words
The memory device of claim 17 further including: a delay locked loop, coupled to the clock receiver circuitry, to generate an internal clock signal using at least the external clock signal; and wherein the plurality of output drivers output data in response to the internal clock signal.
Claim 22
Dependent Claim
23 words
The memory device of claim 17 wherein the memory device outputs data in response to a rising edge of the external clock signal.
Claim 23
Dependent Claim
45 words
The memory device of claim 20 further including: clock generation circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal; and an output driver, coupled to the internal clock generation circuitry, to output the data in response to the internal clock signal.
Claim 24
Dependent Claim
23 words
The memory device of claim 21 wherein the output driver outputs data in response to a rising edge of the internal clock signal.
Claim 25
Independent Claim
89 words
A method of controlling a synchronous memory device having at least one memory section including a plurality of memory cells and a register for storing a value which is representative of a time delay after which the memory device responds to a read request, the method comprising: issuing a read request to the memory device; and receiving data from the memory device, in response to the read request, wherein the memory device outputs the data after the time delay transpires and synchronously with respect to an external clock signal.
Claim 26
Independent Claim
89 words
A method of controlling a synchronous memory device having at least one memory section including a plurality of memory cells and a register for storing a value which is representative of a time delay after which the memory device responds to a read request, the method comprising: issuing a read request to the memory device; and receiving data from the memory device, in response to the read request, wherein the memory device outputs the data after the time delay transpires and synchronously with respect to an external clock signal.
Claim 27
Dependent Claim
29 words
The method of claim 23 further including issuing a control register access, wherein, in response to the control registers access, the memory device stores the value in the register.
Claim 28
Dependent Claim
24 words
The method of claim 24 wherein the control register access and the value are provided to the memory device in a single request packet.
Claim 29
Dependent Claim
36 words
The method of claim 23 wherein the read request and information identifying the time delay after which the memory device responds to a read request are provided to the memory device in a single request packet.
Claim 30
Dependent Claim
34 words
The method of claim 23 further including: initializing the register in the memory device by issuing a control register access on the bus; and providing the value which is representative of the time delay.
Claim 31
Dependent Claim
19 words
The method of claim 23 further including identifying the memory device on the bus using a device identification code.
Claim 32
Dependent Claim
37 words
The method of claim 28 wherein the device identification code and information identifying the time delay after which the memory device responds to a read request are provided to the memory device in a single request packet.
Claim 33
Dependent Claim
15 words
The method of claim 28 wherein the device identification code is a unique device code.
Claim 34
Dependent Claim
15 words
The method of claim 28 wherein the device identification code is a non-unique device code.
Claim 35
Dependent Claim
21 words
The method of claim 23 wherein the value stored in the register is one of a plurality of available delay times.
Claim 36
Dependent Claim
14 words
The method of claim 23 wherein the external clock signal has a fixed frequency.
Claim 37
Dependent Claim
103 words
A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; a register which stores a value which is representative of a number of cycles of the external clock signal to transpire after which the memory device responds to receiving a request to provide data; and a plurality of output drivers to output data in response to receiving a request to provide data, wherein the data is provided after the number of cycles of the external clock signal represented by the value have transpired.
Claim 38
Dependent Claim
103 words
A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; a register which stores a value which is representative of a number of cycles of the external clock signal to transpire after which the memory device responds to receiving a request to provide data; and a plurality of output drivers to output data in response to receiving a request to provide data, wherein the data is provided after the number of cycles of the external clock signal represented by the value have transpired.
Claim 39
Dependent Claim
25 words
The memory device of claim 34 wherein the plurality of output drivers output data synchronously with respect to a transition of the external clock signal.
Claim 40
Dependent Claim
41 words
The memory device of claim 34 further including input receiver circuitry, coupled to the bus, to receive the request to provide data, wherein the request to provide data is sampled from the bus synchronously with respect to the external clock signal.
Claim 41
Dependent Claim
43 words
The memory device of claim 36 wherein the input receiver circuitry further includes a first input latch coupled to the bus, wherein the first input latch samples a first information bit synchronously with respect to a rising edge of the external clock signal.
Claim 42
Dependent Claim
43 words
The memory device of claim 37 wherein the input receiver circuitry further includes a second input latch coupled to the bus, wherein the second input latch samples a second information bit synchronously with respect to a falling edge of the external clock signal.
Claim 43
Dependent Claim
32 words
The memory system of claim 38 the first and second information bits are included in the request to provide data, and wherein the request to provide data includes address and control information.
Claim 44
Dependent Claim
35 words
The memory system of one of claim 34 wherein the request to provide data includes N bits of information and the bus includes M number of signal lines wherein M is substantially less than N.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |