Patent US6034897A successfully refreshed from Google Patents.
US6034897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Space management for managing high capacity nonvolatile memory
Assignee: Micron Technology Inc
•
Filing: 1999-04-01
•
Granted: 2000-03-07
•
Expires: 2019-04-01
Abstract
Abstract In accordance with an embodiment of the present invention, a controller device is disclosed for use in a digital system having a host and nonvolatile memory devices. The controller device is coupled to the host and at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory unit and reads the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information. The controller device erases the digital information stored in the blocks of the nonvolatile memory devices in-parallel form. The controller device includes a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information. The space manager assigns a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, forms 'super' blocks, each 'super' block having blocks arranged inparallel, identifies a particular 'super' block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular 'super' block. The first block within the first nonvolatile memory device is first selected for erasure thereof and an erase operation to be performed on the selected first block is initiated. Thereafter, a second block within the second nonvolatile memory device is selected for erasure thereof and an erase operation to be performed on the selected second block is initiated. Thereafter, the first and second block of the particular 'super' block are erased so that erasure of the second block is performed without waiting for completion of the erasure of the first block. The status of the first and second nonvolatile memory devices is indicated as being busy during erasure of the first and second blocks, wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the 'super' block being arranged in-parallel and overlapping of the erase operations of the blocks within the 'super' blocks thereby increasing the overall performance of the digital system.
Inventors
- 👤 Petro Estakhri
- 👤 Berhanu Iman
- 👤 Min Guo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:31
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/06; G11C16/08; G11C16/10; G11C16/102; G11C16/14; G11C16/16; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
350 words
A method for use in a digital system having a controller device coupled to a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory unit and reading the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information, the method for erasing digital information stored in the blocks of the nonvolatile memory devices inparallel and comprising: (a) assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors; (b) forming `super` blocks, each `super` block having blocks arranged in parallel wherein blocks of the same sequential number in each of the nonvolatile memory devices in like position relative to each other; (c) identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block by the controller; (d) first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof; (e) initiating an erase operation to be performed on the selected first block; (f) second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof; (g) initiating an erase operation to be performed on the selected second block; (h) erasing the first and second block of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and (h) indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second blocks, wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.
Claim 2
Independent Claim
350 words
A method for use in a digital system having a controller device coupled to a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory unit and reading the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information, the method for erasing digital information stored in the blocks of the nonvolatile memory devices inparallel and comprising: (a) assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, each block having a predetermined number of sectors; (b) forming `super` blocks, each `super` block having blocks arranged in parallel wherein blocks of the same sequential number in each of the nonvolatile memory devices in like position relative to each other; (c) identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block by the controller; (d) first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof; (e) initiating an erase operation to be performed on the selected first block; (f) second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof; (g) initiating an erase operation to be performed on the selected second block; (h) erasing the first and second block of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block; and (h) indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second blocks, wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.
Claim 3
Dependent Claim
43 words
A method for use in a digital system as recited in claim 1 further including the steps of setting an erase counter equal to the number of blocks within a `super` block and decrementing the erase counter after each of the initiating steps.
Claim 4
Dependent Claim
40 words
A method for use in a digital system as recited in claim 2 wherein upon the value indicated by the erase counter reaching `0`, checking for completion of the erasure of all of the blocks within the particular `super` block.
Claim 5
Dependent Claim
75 words
A method for use in a digital system as recited in claim 1 wherein during the indicating step, setting a Ready/Busy* signal for indicating that the nonvolatile memory unit is busy upon starting the erase operation on the first nonvolatile memory device and upon completion of the erase operation on the last nonvolatile memory device of the nonvolatile memory unit, resetting the Ready/Busy* signal for indicating that the nonvolatile memory unit is not longer busy.
Claim 6
Dependent Claim
42 words
A method for use in a digital system as recited in claim 1 further including completing erasing of all of the selected blocks within the particular super block and thereafter verifying successful completion of the selected blocks of the particular super block.
Claim 7
Dependent Claim
23 words
A method for use in a digital system as recited in claim 5 wherein said verifying step includes issuing a read status command.
Claim 8
Dependent Claim
45 words
A method for use in a digital system as recited in claim 1 wherein the particular super block includes more than two blocks and selecting the more than two blocks for erasure thereof, erasing the same and upon completion of the erasure, verifying erasure thereof.
Claim 9
Dependent Claim
373 words
A controller device for use in a digital system, the controller device being coupled to a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory unit and reading the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information, the controller device for erasing digital information stored in the blocks of the nonvolatile memory devices in parallel and comprising: a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information, the space manager for assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, for forming `super` blocks, each `super` block having blocks arranged inparallel wherein blocks of the same sequential number in each of the nonvolatile memory devices in like position relative to each other, for identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block, for first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof, for initiating an erase operation to be performed on the selected first block, for second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof, for initiating an erase operation to be performed on the selected second block, erasing the first and second block of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block, and for indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second blocks, wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.
Claim 10
Dependent Claim
373 words
A controller device for use in a digital system, the controller device being coupled to a host and at least two nonvolatile memory devices, the host for storing digital information in the nonvolatile memory unit and reading the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information, the controller device for erasing digital information stored in the blocks of the nonvolatile memory devices in parallel and comprising: a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information, the space manager for assigning a predetermined number of blocks, in sequential order, to each of the nonvolatile memory devices, for forming `super` blocks, each `super` block having blocks arranged inparallel wherein blocks of the same sequential number in each of the nonvolatile memory devices in like position relative to each other, for identifying a particular `super` block having at least two blocks, a first block being located in a first nonvolatile memory device and a second block being located in a second nonvolatile memory device, for erasure of the particular `super` block, for first selecting the first block within the first nonvolatile memory device from the particular `super` block for erasure thereof, for initiating an erase operation to be performed on the selected first block, for second selecting a second block within the second nonvolatile memory device from the particular `super` block for erasure thereof, for initiating an erase operation to be performed on the selected second block, erasing the first and second block of the particular `super` block so that erasure of the second block is performed without waiting for completion of the erasure of the first block, and for indicating the status of the first and second nonvolatile memory devices to be busy during erasure of the first and second blocks, wherein the speed of erase operations in the digital system is substantially increased due to the blocks of the `super` block being arranged in-parallel and overlapping of the erase operations of the blocks within the `super` blocks thereby increasing the overall performance of the digital system.
Claim 11
Dependent Claim
48 words
A controller device for use in a digital system as recited in claim 8 further including a flag field for indicating the status of the particular super block for use in identifying the particular super block as being `old` and ready for erasure thereof by the controller device.
Claim 12
Dependent Claim
66 words
A controller device for use in a digital system as recited in claim 8 further including an erase counter and for setting the erase counter equal to the number of blocks within a `super` block prior to the start of the erase operation on the particular super block and decrementing the erase counter after starting erasure of each of the blocks of the particular super block.
Claim 13
Dependent Claim
45 words
A controller device for use in a digital system as recited in claim 10 wherein upon the value indicated by the erase counter reaching `0`, the controller device for checking for completion of the erasure of all of the blocks within the particular `super` block.
Claim 14
Dependent Claim
22 words
A controller device for use in a digital system as recited in claim 8 wherein the nonvolatile memory devices are flash chips.
References Cited (Backward Citations)
US4210959A
Cited
US4405952A
Cited
US4355376A
Cited
US4616311A
Cited
US4456971A
Cited
US4525839A
Cited
US4450559A
Cited
JPS58215794A
Cited
JPS58215795A
Cited
US4498146A
Cited
WO1984000628A1
Cited
JPS5945695A
Cited
US4710871A
Cited
AU557723B2
Cited
JPS59162695A
Cited
US4896262A
Cited
JPS60212900A
Cited
JPS6196598A
Cited
US4654847A
Cited
US4774700A
Cited
US4920518A
Cited
EP0243503A1
Cited
EP0220718A2
Cited
US4748320A
Cited
US4800520A
Cited
US4746998A
Cited
US4924331A
Cited
US4757474A
Cited
JPS62283497A
Cited
JPS62283496A
Cited
US4953122A
Cited
JPS63183700A
Cited
US5268870A
Cited
US5434825A
Cited
US5544118A
Cited
US5554553A
Cited
US5568439A
Cited
US5168465A
Cited
US5583812A
Cited
US5198380A
Cited
US5642312A
Cited
US5712819A
Cited
US5293560A
Cited
US5268318A
Cited
US4914529A
Cited
US5070474A
Cited
US5297148A
Cited
US5418752A
Cited
US5535328A
Cited
US5719808A
Cited
US5226168A
Cited
US5200959A
Cited
EP0424191A2
Cited
US5303198A
Cited
EP0489204A1
Cited
US5544356A
Cited
US5504760A
Cited
US5369615A
Cited
US5396468A
Cited
US5270979A
Cited
US5663901A
Cited
JPH04332999A
Cited
EP0522780A2
Cited
US5524230A
Cited
US5430859A
Cited
US5471478A
Cited
US5438573A
Cited
US5778418A
Cited
EP0686976A2
Cited
EP0544252A2
Cited
FR2687811A1
Cited
US5532962A
Cited
US5315541A
Cited
US5428621A
Cited
US5337275A
Cited
US5341330A
Cited
US5341339A
Cited
US5357475A
Cited
US5388083A
Cited
US5485595A
Cited
US5479638A
Cited
US5353256A
Cited
US5422842A
Cited
US5532964A
Cited
US5495442A
Cited
US5566314A
Cited
US5534456A
Cited
US5592420A
Cited
US5563825A
Cited
US5693570A
Cited
US5508971A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |