US5535328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells
Assignee: SanDisk Technologies LLC
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Filing: 1995-02-23
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Granted: 1996-07-09
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Expires: 2015-02-23
Abstract
Abstract A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
Inventors
- 👤 Eliyahou Harari
- 👤 Robert D. Norman
- 👤 Sanjay Mehrotra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:35
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/0614; G06F3/0616; G06F3/0628; G06F3/0646; G06F3/0652; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0679; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C29/52; G11C29/70; G11C29/76; G11C29/765; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G06F11/08; G06F11/10; G06F11/1008; G06F11/1068; G06F12/08; G06F12/0802; G06F12/0804; G06F12/12; G06F12/121; G06F12/123; G06F2212/00; G06F2212/31; G06F2212/312; G06F2212/72; G06F2212/7203; G06F2212/7207; G06F3/0662; G06F3/0664; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C2211/563; G11C2211/5634; G11C2211/564; G11C2211/5643; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
151 words
A memory card connectable to a computer system, said memory card comprising: an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, the individual sectors including a user data portion and a spare portion of the group of memory cells, a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system, means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors, and means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors.
Claim 2
Dependent Claim
151 words
A memory card connectable to a computer system, said memory card comprising: an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, the individual sectors including a user data portion and a spare portion of the group of memory cells, a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system, means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors, and means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors.
Claim 3
Dependent Claim
41 words
The memory card of claim 1, which additionally comprises means within said memory controller for, upon detecting a defective sector having more than a predetermined number of defective cells therein, substituting another of said plurality of sectors for the defective sector.
Claim 4
Dependent Claim
43 words
The memory card of claim 1, which additionally comprises means within said memory controller for storing and accessing error correction codes in the spare portions of the sectors which are related to data stored in the user data portions of the same sectors.
Claim 5
Dependent Claim
29 words
The memory card of claim 1, wherein said memory card is compatible with a magnetic disk drive storage system and capable of being substituted therefor in said computer system.
Claim 6
Independent Claim
177 words
A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising: providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system, reserving a portion of the memory cells within the individual sectors as spare cells, remaining cells of the individual sectors being designated for storing data, enabling the controller to detect when a cell within the data portion of a sector becomes defective, causing the controller to store an address of such a detected defective cell, and thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected.
Claim 7
Independent Claim
177 words
A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising: providing said memory array and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system, reserving a portion of the memory cells within the individual sectors as spare cells, remaining cells of the individual sectors being designated for storing data, enabling the controller to detect when a cell within the data portion of a sector becomes defective, causing the controller to store an address of such a detected defective cell, and thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected.
Claim 8
Dependent Claim
39 words
The method according to claim 5, wherein the storage of an address of a detected defective cell includes storing the address of the detected defective cell within the spare cells of the sector in which the defective cell exists.
Claim 9
Dependent Claim
29 words
The method according to claim 6, wherein detecting the address of a defective cell includes maintaining a defect map which links addresses of defective cells to substitute redundant cells.
Claim 10
Dependent Claim
23 words
The method according to claim 7, wherein detecting the address of a defective cell includes storing the defect map in the memory array.
Claim 11
Dependent Claim
66 words
The method according to claim 5, additionally comprising: reserving a number of the sectors as redundant sectors, in response to a number of occurrences of a defective cell being detected within a single sector exceeding a predetermined number, marking such a single sector as a defective sector, and thereafter remapping the defective sector into one of the redundant sectors as a substitute for the defective sector.
Claim 12
Dependent Claim
55 words
The method according to claim 9, wherein the marking of a sector as the defective sector includes placing an address of the defective sector into a defect map that includes an address of the substitute redundant sector, thereby causing the redundant sector to be accessed in response to a request to access the defective sector.
Claim 13
Dependent Claim
17 words
The method according to claim 9, wherein a defect map is stored in the memory cell array.
Claim 14
Dependent Claim
20 words
The method according to claim 9, wherein the marking and remapping operations are under the control of said memory controller.
Claim 15
Dependent Claim
25 words
The method according to claim 5, additionally comprising storing addresses of the sectors in the spare cells of the sectors to which the address pertains.
Claim 16
Dependent Claim
30 words
The method according to claim 5, additionally comprising storing in the spare cells of the individual sectors an error correction code for data stored in corresponding ones of the sectors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |