Ball grid array semiconductor package

Claim 2

A semiconductor package, comprising: a heat spreader for dissipating heat; a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive, the ground plane having a first aperture opening exposing a surface of the heat spreader, the first aperture being configured to receive a semiconductor die; an interconnect substrate being adhesively attached to the ground plane, the interconnect substrate only having a single metal layer and having a complementary second aperture over the first aperture of the ground plane, and the single metal layer of the interconnect substrate having a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package; and at least one conductively filled via defined through the interconnect substrate and in electrical contact with the ground plane to define direct ground connections from selected ones of the plurality of metal patterns of the interconnect substrate; wherein the ground plane includes patterned wettable plating pads over selected regions that are in contact with the at least one conductively filled via defined through the interconnect substrate.

Claim 3

A semiconductor package as recited in claim 1, wherein the at least one conductively filled via is solder filled and reflowed to establish a metallurgical bond to the ground plane.

Claim 4

A semiconductor package as recited in claim 1, wherein the complementary second aperture of the interconnect substrate is larger than the first aperture of the ground plane.

Claim 5

A semiconductor package as recited in claim 3, wherein a plated ground ring is defined around the first aperture of the ground plane and extending substantially to the complementary second aperture of the interconnect substrate.

Claim 6

A semiconductor package as recited in claim 1, wherein a plurality of solder balls are attached to wettable ball pads defined by the plurality of metal patterns on the interconnect substrate such that selected solder balls are in contact with the least one conductively filled via defined through the interconnect substrate.

Claim 7

A semiconductor package as recited in claim 5, wherein a plurality of metal traces are defined by the plurality of metal patterns on the interconnect substrate, the plurality of metal traces being configured to interconnect the wettable ball pads to the semiconductor die.

Claim 8

A semiconductor package as recited in claim 6, wherein the metal traces leading from the wettable ball pads terminate in bonding fingers, and a plurality of bond wires interconnect the bonding fingers to the semiconductor die.

Claim 9

A semiconductor package as recited in claim 6, wherein the at least one conductively filled via is located in a substantially outer peripheral location of the interconnect substrate, such that the solder ball in contact with the at least one conductively filled via need not be routed by the plurality of metal traces.

Claim 10

A semiconductor package as recited in claim 8, wherein the at least one conductively filled via enables the construction of a higher density solder ball package.

Claim 11

A semiconductor package as recited in claim 4, wherein at least one bonding wire is used to interconnect the semiconductor die to the plated ground ring defined around the first aperture of the ground plane.

Claim 12

A semiconductor package as recited in claim 5, wherein the plurality of metal patterns of interconnect substrate are sandwiched between a first dielectric layer and a second dielectric layer such that the first dielectric layer is adhesively attached to the ground plane.

Claim 13

A semiconductor package as recited in claim 11, wherein the second dielectric layer is a solder mask having pad openings for receiving solder balls.

Claim 14

A semiconductor package as recited in claim 7, wherein an encapsulant material covers the semiconductor die and the a plurality of bond wires interconnect the bonding fingers to the semiconductor chip, the encapsulation material is configured to be a predetermined distance below a crown of the solder balls.

Claim 15

A semiconductor package as recited in claim 7, wherein a lid covers the semiconductor die and the a plurality of bond wires interconnect the bonding fingers to the semiconductor chip.

Claim 16

A semiconductor package as recited in claim 6, wherein a power ring is defined by the plurality of metal patterns on the interconnect substrate, the power ring arranged to surround the complementary second aperture of the interconnect substrate.

Claim 17

A semiconductor package as recited in claim 1, wherein the heat spreader is a metal selected from the group of copper, copper/tungsten/copper laminate, and copper/molybdenum/copper laminate.

Claim 18

A semiconductor package as recited in claim 16, wherein the heat spreader metal is treated with one of a black copper oxide and a nickel plating having a thickness of between about 1 and 7 microns thick to improve the adhesiveness of the heat spreader.

Claim 19

A semiconductor package as recited in claim 1, wherein the ground plane is a copper metal.

Claim 20

A semiconductor package as recited in claim 18, wherein the copper metal of the ground plane is selectively plated with a plating material selected from the group consisting of gold and silver.

Claim 21

A semiconductor package as recited in claim 1, wherein the semiconductor die is electrically attached to the surface of the heat spreader with a silver filled die attach epoxy.

Claim 22

A semiconductor package as recited in claim 1, wherein the electrically insulating adhesive that attaches the first side of the ground plane to the heat spreader is one of a pressure sensitive adhesive and a b-stage epoxy that are in a tape form.

Claim 23

A semiconductor package as recited in claim 1, wherein the interconnect substrate is adhesively attached to the ground plane with one of a pressure sensitive tape adhesive and a b-stage epoxy tape.

Claim 24

A semiconductor package as recited in claim 1, wherein the interconnect substrate is adhesively attached to the ground plane with a screen printed liquid epoxy.

Claim 25

A semiconductor package as recited in claim 1, wherein the semiconductor package including the heat spreader, the ground plane and the interconnect substrate has a thickness of about 1.0 mm or smaller.

Claim 26

A semiconductor package as recited in claim 1, wherein the semiconductor package is a ball grid array package having a cavity down orientation.

Claim 27

A flip chip semiconductor package, comprising: a heat spreader for dissipating heat generated within the semiconductor package; a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive, the ground plane having a first aperture exposing a surface of the heat spreader; a first side of a semiconductor die attached to the heat spreader surface defined by the first aperture, a second side of the semiconductor die having a plurality of input/output pads that are in electrical contact with a plurality of solder bumps; an interconnect substrate adhesively attached to the ground plane, the interconnect substrate having a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package, the plurality of metal patterns including a plurality of metal bump pads that are configured to meet associated ones of the plurality of solder bumps on the second side of the semiconductor die, the interconnect substrate only having one metal layer; and a conductively filled via defined through the interconnect substrate and in electrical contact with the ground plane to define direct ground connections from selected ones of the plurality of metal patterns of the interconnect substrate; wherein the ground plane includes patterned wettable plating pads over selected regions that are in contact with the conductively filled via defined through the interconnect substrate, and the semiconductor package including the heat spreader, the ground plane and the interconnect substrate has a thickness of about 1.0 mm or smaller.

Claim 28

A flip chip semiconductor package, comprising: a heat spreader for dissipating heat generated within the semiconductor package; a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive, the ground plane having a first aperture exposing a surface of the heat spreader; a first side of a semiconductor die attached to the heat spreader surface defined by the first aperture, a second side of the semiconductor die having a plurality of input/output pads that are in electrical contact with a plurality of solder bumps; an interconnect substrate adhesively attached to the ground plane, the interconnect substrate having a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package, the plurality of metal patterns including a plurality of metal bump pads that are configured to meet associated ones of the plurality of solder bumps on the second side of the semiconductor die, the interconnect substrate only having one metal layer; and a conductively filled via defined through the interconnect substrate and in electrical contact with the ground plane to define direct ground connections from selected ones of the plurality of metal patterns of the interconnect substrate; wherein the ground plane includes patterned wettable plating pads over selected regions that are in contact with the conductively filled via defined through the interconnect substrate, and the semiconductor package including the heat spreader, the ground plane and the interconnect substrate has a thickness of about 1.0 mm or smaller.

Claim 29

A flip chip semiconductor package as recited in claim 26, wherein the conductively filled via is solder filled and reflowed to establish a metallurgical bond to the ground plane.

Claim 30

A flip chip semiconductor package as recited in claim 26, wherein a plurality of solder balls are attached to wettable ball pads defined by the plurality of metal patterns on the interconnect substrate such that at least one solder ball is in contact with the conductively filled via defined through the interconnect substrate.

Claim 31

A flip chip semiconductor package as recited in claim 28, wherein a plurality of metal traces are defined by the plurality of metal patterns on the interconnect substrate, the plurality of metal traces being configured to interconnect the wettable ball pads to the plurality of metal bump pads that arc in electrical contact with the plurality of solder bumps on the semiconductor die.

Claim 32

A flip chip semiconductor package as recited in claim 29, wherein the conductively filled via is located in a substantially outer peripheral location of the interconnect substrate, such that the solder ball in contact with the conductively filled via need not be routed by the plurality of metal traces.

Claim 33

A flip chip semiconductor package as recited in claim 26, wherein the conductively filled via enables the construction of a higher density ball grid array package.

Claim 34

A flip chip semiconductor package as recited in claim 30, wherein the plurality of metal patterns of interconnect substrate are sandwiched between an adhesive layer that is attached to the ground plane and a dielectric layer.

Claim 35

A flip chip semiconductor package as recited in claim 32, wherein the dielectric layer is a solder mask having pad openings for receiving solder balls.

Claim 36

A flip chip semiconductor package as recited in claim 26, wherein the heat spreader is a metal selected from the group consisting of a copper metal, copper/tungsten/copper laminate metal, and a copper/molybdenum/copper laminate metal.

Claim 37

A flip chip semiconductor package as recited in claim 34, wherein the heat spreader metal is treated with one of a black copper oxide and a nickel plating having a respective thickness of between about 1 micron and 7 microns for increased adhesiveness.

Claim 38

A flip chip semiconductor package as recited in claim 26, wherein the ground plane is a copper metal.

Claim 39

A flip chip semiconductor package as recited in claim 36, wherein the copper metal of the ground plane is selectively plated with a plating material selected from the group consisting of gold and silver.

Claim 40

A flip chip semiconductor package as recited in claim 26, wherein the first side of the semiconductor die is electrically attached to the surface of the heat spreader with a silver filled die attach epoxy.

Claim 41

A flip chip semiconductor package as recited in claim 26, wherein the electrically insulating adhesive that attaches the first side of the ground plane to the heat spreader is one of a pressure sensitive adhesive and a b-stage epoxy.

Claim 42

A flip chip semiconductor package as recited in claim 32, wherein the adhesive layer is one of a pressure sensitive tape adhesive and a b-stage epoxy tape.

Claim 43

A flip chip semiconductor package as recited in claim 26, wherein the semiconductor package is a ball grid array package having a cavity down orientation.

Claim 44

A semiconductor package, comprising: a heat spreading means for dissipating heat; a ground plane means having a first side that is attached to the heat spreading means with an electrically insulating adhesive means, the ground plane having a first aperture opening exposing a surface of the heat spreading means, the first aperture being configured to receive a semiconductor die; an interconnect substrate means having only one metal layer, the interconnect substrate means being attached to the ground plane and having a complementary second aperture over the first aperture of the ground plane means, and the interconnect substrate means having a plurality of metal pattern means for electrically interconnecting the semiconductor die to electrical connection means that are external to the semiconductor package; and at least one conductively filled via means defined through the interconnect substrate means and in electrical contact with the ground plane means to define direct ground connections from selected ones of the plurality of metal pattern means of the interconnect substrate means; wherein the ground plane means includes patterned wettable plating means over selected regions that are in contact with the at least one conductively filled via means defined through the interconnect substrate means, and the complementary second aperture of the interconnect substrate means is larger than the first aperture of the ground plane means.

Claim 45

A semiconductor package, comprising: a heat spreading means for dissipating heat; a ground plane means having a first side that is attached to the heat spreading means with an electrically insulating adhesive means, the ground plane having a first aperture opening exposing a surface of the heat spreading means, the first aperture being configured to receive a semiconductor die; an interconnect substrate means having only one metal layer, the interconnect substrate means being attached to the ground plane and having a complementary second aperture over the first aperture of the ground plane means, and the interconnect substrate means having a plurality of metal pattern means for electrically interconnecting the semiconductor die to electrical connection means that are external to the semiconductor package; and at least one conductively filled via means defined through the interconnect substrate means and in electrical contact with the ground plane means to define direct ground connections from selected ones of the plurality of metal pattern means of the interconnect substrate means; wherein the ground plane means includes patterned wettable plating means over selected regions that are in contact with the at least one conductively filled via means defined through the interconnect substrate means, and the complementary second aperture of the interconnect substrate means is larger than the first aperture of the ground plane means.

Claim 46

A semiconductor package as recited in claim 42, wherein the at least one conductively filled via means is solder filled and reflowed to establish a metallurgical bond to the ground plane.

Claim 47

A semiconductor package as recited in claim 42, wherein a plated ground ring means is defined around the first aperture of the ground plane means and extends substantially within the complementary second aperture of the interconnect substrate means.