Abstract A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.
A semiconductor chip package comprising: a semiconductor chip of the type having a plurality of individual solder ball connections on a mounting surface thereof; and a laminated substrate having at least a conductive core layer and at least one lamina formed on the core layer; wherein each lamina has a dielectric layer and a conductive layer, said dielectric layer being formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material; wherein at least one via extends through said at least one lamina, said via having an entrance aperture in the conductive layer of <75 μm and an aspect ratio of between 3:1 and 25:1; and wherein said laminated substrate includes a plurality of individual pads to which the individual solder ball connections of said semiconductor chip is connected.
Claim 2
Dependent Claim
134 words
A semiconductor chip package comprising: a semiconductor chip of the type having a plurality of individual solder ball connections on a mounting surface thereof; and a laminated substrate having at least a conductive core layer and at least one lamina formed on the core layer; wherein each lamina has a dielectric layer and a conductive layer, said dielectric layer being formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material; wherein at least one via extends through said at least one lamina, said via having an entrance aperture in the conductive layer of <75 μm and an aspect ratio of between 3:1 and 25:1; and wherein said laminated substrate includes a plurality of individual pads to which the individual solder ball connections of said semiconductor chip is connected.
Claim 3
Dependent Claim
13 words
The semiconductor chip package of claim 1, wherein said fluoropolymer material is polytetrafluoroethytene.
Claim 4
Dependent Claim
25 words
The semiconductor chip package of claim 1, wherein the polytetrafluoroethylene material is an expanded polytetrafluoroethylene matrix containing a mixed cyanate ester-epoxy adhesive and inorganic filler.