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US6018196A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor flip chip package

Assignee: W.L. Gore and Associates Inc
•
Filing: 1999-02-26
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Granted: 2000-01-25
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Expires: 2019-02-26
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Abstract

Abstract A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.

Inventors

  • 👤 David B. Noddin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 17:07
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/0011; H05K3/0017; H05K3/0026; H05K3/0032; H05K3/0038; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/095; H05K2201/00; H05K2201/01; H05K2201/0104; H05K2201/0112; H05K2203/00; H05K2203/13; H05K2203/1377; H05K2203/1383; H05K3/0035; H05K3/40; H05K3/42; H05K3/425; H05K3/427; H05K3/429; H05K3/46; H05K3/4644; H05K3/4652; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 134 words
A semiconductor chip package comprising: a semiconductor chip of the type having a plurality of individual solder ball connections on a mounting surface thereof; and a laminated substrate having at least a conductive core layer and at least one lamina formed on the core layer; wherein each lamina has a dielectric layer and a conductive layer, said dielectric layer being formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material; wherein at least one via extends through said at least one lamina, said via having an entrance aperture in the conductive layer of <75 μm and an aspect ratio of between 3:1 and 25:1; and wherein said laminated substrate includes a plurality of individual pads to which the individual solder ball connections of said semiconductor chip is connected.
Claim 2
Dependent Claim 134 words
A semiconductor chip package comprising: a semiconductor chip of the type having a plurality of individual solder ball connections on a mounting surface thereof; and a laminated substrate having at least a conductive core layer and at least one lamina formed on the core layer; wherein each lamina has a dielectric layer and a conductive layer, said dielectric layer being formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material; wherein at least one via extends through said at least one lamina, said via having an entrance aperture in the conductive layer of <75 μm and an aspect ratio of between 3:1 and 25:1; and wherein said laminated substrate includes a plurality of individual pads to which the individual solder ball connections of said semiconductor chip is connected.
Claim 3
Dependent Claim 13 words
The semiconductor chip package of claim 1, wherein said fluoropolymer material is polytetrafluoroethytene.
Claim 4
Dependent Claim 25 words
The semiconductor chip package of claim 1, wherein the polytetrafluoroethylene material is an expanded polytetrafluoroethylene matrix containing a mixed cyanate ester-epoxy adhesive and inorganic filler.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-01-24 2003-07-26 2004-01-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-01-24 2007-07-26 2008-01-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-01-24 2011-07-26 2012-01-25 $7700.00 Window Closed / Lapsed

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