US5999726A — Connectivity-based approach for extracting layout…

Claim 1

Independent Claim 85 words

A computer implemented method of extracting characteristics of an integrated circuit design comprising: providing a netlist database input for a circuit block of the integrated circuit design; providing a layout database input for the circuit block of the integrated circuit design; generating a connectivity database, wherein in the connectivity database, geometries for the circuit block from the layout database are referenced by corresponding nets for the circuit block from the netlist database; and extracting layout parasitics for at least one net in the connectivity database.

Claim 2

Dependent Claim 85 words

A computer implemented method of extracting characteristics of an integrated circuit design comprising: providing a netlist database input for a circuit block of the integrated circuit design; providing a layout database input for the circuit block of the integrated circuit design; generating a connectivity database, wherein in the connectivity database, geometries for the circuit block from the layout database are referenced by corresponding nets for the circuit block from the netlist database; and extracting layout parasitics for at least one net in the connectivity database.

Claim 3

Dependent Claim 18 words

The method of claim 1 further comprising: extracting layout parasitics for the circuit block on a net-by-net basis.

Claim 4

Dependent Claim 20 words

The method of claim 1 further comprising: extracting layout parasitics for the entire integrated circuit design on a net-by-net basis.

Claim 5

Dependent Claim 17 words

The method of claim 1 wherein the netlist database is generated by using a schematic capture program.

Claim 6

Dependent Claim 14 words

The method of claim 1 wherein the netlist database is manually or computer generated.

Claim 7

Dependent Claim 15 words

The method of claim 1 wherein generating a connectivity database comprises processing an LVS file.

Claim 8

Dependent Claim 21 words

The method of claim 1 wherein the extracting layout parasitics determines parasitic resistances and parasitic capacitances for the integrated circuit design.

Claim 9

Dependent Claim 54 words

The method of claim 1 wherein extracting layout parasitics comprises: extracting parasitic capacitances for a first cross-section of a selected net; extracting parasitic capacitances for a second cross-section, transverse to the first cross-section, of the selected net; and calculating a sum of the parasitic capacitances extracted for the first cross-section and the second cross-section.

Claim 10

Dependent Claim 39 words

The method of claim 8 wherein extracting layout parasitics further comprises: calculating a quasi-three-dimensional parasitic capacitance value for the net by subtracting from the sum a value representative of layout parasitics extracted in both the first and second cross-sections.

Claim 11

Dependent Claim 38 words

The method of claim 8 wherein extracting layout parasitics further comprises: calculating a quasi-three-dimensional parasitic capacitance value for the net by subtracting from the sum a capacitance value of an overlap area of the first and second cross-sections.

Claim 12

Dependent Claim 47 words

The method of claim 1 wherein extracting layout parasitics comprises: decomposing a selected net into polygon subsections; determining a parasitic resistance of each of the polygon subsections; and adding together parasitic resistances for each of the polygon subsections to determine a total resistance for the selected net.

Claim 13

Dependent Claim 90 words

The method of claim 1 wherein extracting layout parasitics comprises: extracting parasitic capacitances for a first cross-section of a selected net; extracting parasitic capacitances for a second cross-section, transverse to the first cross-section, of the selected net; calculating a sum of the parasitic capacitances extracted for the first cross-section and the second cross-section; decomposing the selected net into polygon subsections; determining a parasitic resistance of each of the polygon subsections; and adding together parasitic resistances for each of the polygon subsections to determine a total resistance for the selected net.

Claim 14

Independent Claim 59 words

A method of designing an integrated circuit comprising: providing a schematic database; providing a layout database corresponding to the schematic database; generating a connectivity database, wherein in the connectivity database, geometries of the layout database are referenced and organized by corresponding nets of the schematic database; and extracting layout parasitics for at least one net in the connectivity database.

Claim 15

Independent Claim 59 words

A method of designing an integrated circuit comprising: providing a schematic database; providing a layout database corresponding to the schematic database; generating a connectivity database, wherein in the connectivity database, geometries of the layout database are referenced and organized by corresponding nets of the schematic database; and extracting layout parasitics for at least one net in the connectivity database.

Claim 16

Dependent Claim 23 words

The method of claim 13 further comprising: using the connectivity database to provide multiple signal race condition analysis of the integrated circuit design.

Claim 17

Dependent Claim 20 words

The method of claim 13 further comprising: using the connectivity database to provide timing analysis of the integrated circuit design.

Claim 18

Dependent Claim 21 words

The method of claim 13 further comprising: using the connectivity database to provide critical path analysis of the integrated circuit design.

Claim 19

Dependent Claim 27 words

The method of claim 13 further comprising: using the connectivity database to provide analysis of coupling effects between digital and analog sections of the integrated circuit design.

Claim 20

Dependent Claim 33 words

The method of claim 13 wherein each net in the connectivity database is specified by a net name or a net number, and each geometry in the connectivity database is specified by coordinates.

Claim 21

Dependent Claim 23 words

The method of claim 13 wherein an entry in the connectivity database comprises an identified net and geometries associated with the identified net.

Claim 22

Dependent Claim 31 words

The method of claim 13 wherein the generating a connectivity database comprises processing an LVS database to arrange each net of the LVS database by layout coordinates of the LVS database.

Claim 23

Dependent Claim 20 words

The method of claim 13 further comprising: using the connectivity database to provide electromigration analysis of the integrated circuit design.

Claim 24

Dependent Claim 21 words

The method of claim 13 further comprising: using the connectivity database to provide power net analysis of the integrated circuit design.

Claim 25

Dependent Claim 21 words

The method of designing an integrated circuit of claim 13 further comprising: backannotating the extracted layout parasitics into the design schematic.

Claim 26

Dependent Claim 86 words

The method of designing an integrated circuit of claim 13 wherein the extracting layout parasitics comprises: choosing at least one selected net from the plurality of nets; decomposing the at least one selected net into polygon subsections; from the decomposed polygon subsections, determining layout parasitics for one of the at least one selected net of the design schematic of the plurality of nets; and repeating the determining layout parasitics until layout parasitics for the at least one selected net of the design schematic have been calculated.

Claim 27

Dependent Claim 71 words

The method of designing an integrated circuit of claim 24 wherein decomposing the at least one selected net comprises: determining a width, W, of a regular polygon touching an irregular polygon; and creating a polygon subsection including the irregular polygon and portions of the regular polygon extending approximately a distance of W/2 in at least two directions from the irregular polygon, wherein the polygon subsection accounts for equipotential lines of current.

Claim 28

Dependent Claim 84 words

The method of designing an integrated circuit of claim 13 wherein the extracting layout parasitics comprises: choosing a selected net from the plurality of nets of the design schematic; determining layout resistance parasitics for the selected net of the plurality of nets of the design schematic; determining layout capacitance parasitics for the selected net of the plurality of nets of the design schematic; and repeating determining layout resistance parasitics and determining capacitance parasitics until parasitics for nets of the design schematic have been extracted.

Claim 29

Dependent Claim 21 words

The method of claim 13 further comprising: using the connectivity database to provide clock skew analysis of the integrated circuit design.

Claim 30

Dependent Claim 70 words

A computer-implemented method of extracting characteristics of an integrated circuit design comprising: providing a netlist database input for the integrated circuit design; providing a layout database input for the integrated circuit design; generating a connectivity database, wherein in the connectivity database, geometries of the layout database are referenced and organized by corresponding nets of the netlist database; and extracting layout parasitics for at least one net in the connectivity database.

Claim 31

Dependent Claim 70 words

A computer-implemented method of extracting characteristics of an integrated circuit design comprising: providing a netlist database input for the integrated circuit design; providing a layout database input for the integrated circuit design; generating a connectivity database, wherein in the connectivity database, geometries of the layout database are referenced and organized by corresponding nets of the netlist database; and extracting layout parasitics for at least one net in the connectivity database.

Claim 32

Dependent Claim 12 words

The method of claim 28 wherein the netlist database is computer generated.

Claim 33

Dependent Claim 14 words

The method of claim 28 wherein the netlist database is manually or computer generated.

Claim 34

Dependent Claim 30 words

The method of claim 28 wherein generating a connectivity database comprises processing a layout-versus-schematic database to arrange each net of the layout-versus-schematic database by layout coordinates of the layout-versus-schematic database.

Claim 35

Dependent Claim 15 words

The method of claim 28 wherein generating a connectivity database comprises processing an LVS file.

Claim 36

Dependent Claim 21 words

The method of claim 28 wherein the extracting layout parasitics determines parasitic resistance and parasitic capacitances for the integrated circuit design.

Claim 37

Dependent Claim 54 words

The method of claim 28 wherein extracting layout parasitics comprises: extracting parasitic capacitances for a first cross-section of a selected net; extracting parasitic capacitances for a second cross-section, transverse to the first cross-section, of the selected net; and calculating a sum of the parasitic capacitances extracted for the first cross-section and the second cross-section.

Claim 38

Dependent Claim 39 words

The method of claim 34 wherein extracting layout parasitics further comprises: calculating a quasi-three-dimensional parasitic capacitance value for the net by subtracting from the sum a value representative of layout parasitics extracted in both the first and second cross-sections.

Claim 39

Dependent Claim 38 words

The method of claim 34 wherein extracting layout parasitic further comprises: calculating a quasi-three-dimensional parasitic capacitance value for the net by subtracting from the sum a capacitance value of an overlap area of the first and second cross-sections.

Claim 40

Dependent Claim 47 words

The method of claim 28 wherein extracting layout parasitics comprises: decomposing a selected net into polygon subsections; determining a parasitic resistance of each of the polygon subsections; and adding together parasitic resistances for each of the polygon subsections to determine a total resistance for the selected net.

Claim 41

Dependent Claim 19 words

The method of claim 28 wherein extracting layout parasitics comprises: generating a distributed RC model for a selected net.

Claim 42

Dependent Claim 15 words

The method of claim 28 wherein extracting layout parasitics accounts for equipotential lines of current.

Claim 43

Dependent Claim 14 words

The method of claim 28 wherein extracting layout parasitics proceeds on a net-by-net basis.

Claim 44

Dependent Claim 16 words

The method of claim 28 further comprising: backannotating the extracted layout parasitics for a circuit simulator.

Claim 45

Dependent Claim 18 words

The method of claim 28 wherein the connectivity database provides a layout connectivity of the integrated circuit design.

Claim 46

Dependent Claim 25 words

The method of claim 28 further comprising: using the connectivity database, displaying on a computer display a selected net of the layout in highlighted form.

Claim 47

Dependent Claim 13 words

The method of claim 28 wherein the netlist database comprises a circuit netlist.

Claim 48

Dependent Claim 12 words

The method of claim 28 wherein the layout database is hierarchically organized.

Claim 49

Dependent Claim 12 words

The method of claim 28 wherein the netlist database is hierarchically organized.

Claim 50

Dependent Claim 20 words

The method of claim 28 further comprising using the extracted layout parasitics to analyze characteristics of the integrated circuit design.

Claim 51

Dependent Claim 24 words

The method of claim 28 wherein extracting layout parasitics comprises determining parasitic capacitances and parasitic resistances of interconnect lines of the integrated circuit design.

Claim 52

Dependent Claim 13 words

The method of claim 28 wherein the netlist database contains a transistor netlist.

Claim 53

Dependent Claim 20 words

The method of claim 28 wherein the extracted layout parasitics are used to evaluate timing parameters of the integrated circuit.

Claim 54

Dependent Claim 17 words

The method of claim 28 wherein the netlist database is generated by using a schematic capture program.

Claim 55

Dependent Claim 92 words

A computer program product comprising a computer-usable medium with computer readable code for causing extraction of integrated circuit parasitics, the computer program product comprising: computer readable code configured to cause a computer to effect generating a connectivity database from a netlist database input and layout database input, wherein in the connectivity database, geometries of the layout database and layout database are organized by corresponding nets of the netlist database; and computer readable code configured to cause a computer to effect extracting layout parasitics for at least one net using the connectivity database.

Claim 56

Dependent Claim 92 words

A computer program product comprising a computer-usable medium with computer readable code for causing extraction of integrated circuit parasitics, the computer program product comprising: computer readable code configured to cause a computer to effect generating a connectivity database from a netlist database input and layout database input, wherein in the connectivity database, geometries of the layout database and layout database are organized by corresponding nets of the netlist database; and computer readable code configured to cause a computer to effect extracting layout parasitics for at least one net using the connectivity database.

Claim 57

Dependent Claim 30 words

The computer program product of claim 52 wherein the computer readable code is configured to cause a computer to effect extracting layout parasitics to determine parasitic resistances and parasitic capacitances.

Claim 58

Independent Claim 65 words

A method of extracting layout parasitics of an integrated circuit comprising: generating a connectivity database, wherein in the connectivity database, geometries of an integrated circuit layout are organized by corresponding nets of an integrated circuit netlist; and extracting layout parasitics of the integrated circuit on a net-by-net basis using the connectivity database, wherein the extracted layout parasitics includes parasitic resistance values and parasitic capacitance values.

Claim 59

Independent Claim 65 words

A method of extracting layout parasitics of an integrated circuit comprising: generating a connectivity database, wherein in the connectivity database, geometries of an integrated circuit layout are organized by corresponding nets of an integrated circuit netlist; and extracting layout parasitics of the integrated circuit on a net-by-net basis using the connectivity database, wherein the extracted layout parasitics includes parasitic resistance values and parasitic capacitance values.

Claim 60

Dependent Claim 75 words

The method of claim 54 wherein extraction of parasitic capacitance values comprises: determining a first parasitic capacitance value for a net using a first cross-section of the integrated circuit; determining a second parasitic value for the net using a second cross-section of the integrated circuit, where the second cross-section is transverse to the first cross-section; and adding the first parasitic capacitance value and second parasitic capacitance value together to obtain a third parasitic capacitance value.

Claim 61

Dependent Claim 30 words

The method of claim 55 wherein extraction of parasitic capacitance values further comprises: subtracting from the third parasitic capacitance value an overlap value to obtain a fourth parasitic capacitance value.

Claim 62

Dependent Claim 15 words

The method of claim 54 wherein the connectivity database is generated using an LVS file.

Claim 63

Independent Claim 54 words

A method of determining layout parasitics comprising: extracting layout parasitics for a first cross-section of a net; extracting layout parasitics for a second cross-section of the net, wherein the second cross-section is transverse to the first cross-section; and calculating a sum of the layout parasitics extracted for the first cross-section and the second cross-section.

Claim 64

Independent Claim 54 words

A method of determining layout parasitics comprising: extracting layout parasitics for a first cross-section of a net; extracting layout parasitics for a second cross-section of the net, wherein the second cross-section is transverse to the first cross-section; and calculating a sum of the layout parasitics extracted for the first cross-section and the second cross-section.

Claim 65

Dependent Claim 35 words

The method of claim 58 further comprising: calculating a quasi-three-dimensional parasitic value by subtracting from the sum a value representative of layout parasitics which are extracted in both the first cross-section and the second cross-section.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-12-06	2003-06-07	2003-12-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-12-06	2007-06-07	2007-12-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-12-06	2011-06-07	2011-12-07	$7700.00	Window Closed / Lapsed

Connectivity-based approach for extracting layout parasitics

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag