Patent US5998864A successfully refreshed from Google Patents.
US5998864A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacking semiconductor devices, particularly memory chips
Assignee: FormFactor Inc
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Filing: 1997-05-27
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Granted: 1999-12-07
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Expires: 2017-05-27
Abstract
Abstract High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., a nickel plating).
Inventors
- 👤 Igor Y. Khandros
- 👤 David V. Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:13
CPC Classifications
B; B23; B23K; B23K20/00; B23K20/002; B23K20/004; G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07364; G01R1/07378; H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/325; H05K3/326; H05K3/40; H05K3/4007; H05K3/4015; H10; H10P; H10P74/00; H10P74/23; H10W; H10W70/00; H10W70/099; H10W72/00; H10W72/071; H10W72/075; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W90/00; H10W90/701; B23K2101/00; B23K2101/36; B23K2101/40; G01R31/00; G01R31/28; G01R31/2851; G01R31/2886; H05K1/00; H05K1/02; H05K1/14; H05K1/141; H05K2201/00; H05K2201/10; H05K2201/10227; H05K2201/1031; H05K2201/10318; H05K2201/10613; H05K2201/10742; H05K2201/1075; H05K2201/10757; H05K2201/10878; H05K2201/10886; H05K2201/10909; H05K2201/10946; H05K3/10; H05K3/20; H05K3/34; H05K3/341; H05K3/3421; H05K3/36; H05K3/368; H10W72/01; H10W72/012; H10W72/01221; H10W72/01225; H10W72/072; H10W72/07231; H10W72/07236; H10W72/07251; H10W72/07531; H10W72/07532; H10W72/20; H10W72/251; H10W72/252; H10W72/255; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/851; H10W72/853; H10W72/856; H10W90/20; H10W90/22; H10W90/24; H10W90/297; H10W90/751; H10W90/754; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
251 words
A semiconductor package assembly, comprising: an interconnection substrate having a plurality of terminals; a first bare semiconductor device having a front surface and a back surface, and also comprising a plurality of terminals on the front surface; a second bare semiconductor device stacked atop the first semiconductor device having a front surface and a back surface, and also comprising a plurality of terminals on the front surface, each of the first and second bare semiconductor devices having a front surface and a back surface; the second bare semiconductor device disposed in an offset stacked manner so that the front surface of the second bare semiconductor device is adjacent the back surface of the first bare semiconductor device, and an edge portion of the second bare semiconductor device is exposed beyond an edge of the first bare semiconductor device; a first set of elongate interconnection elements extending from the terminals on the front surface of the first bare semiconductor device, said first set of elongate interconnection elements having free ends contacting a first portion of the plurality of terminals on the interconnection substrate; and a second set of elongate interconnection elements extending from the terminals on the front surface of the second bare semiconductor device, said terminals disposed in the edge portion of the second bare semiconductor device, said second set of elongate interconnection elements having free ends contacting a second portion of the plurality of terminals on the interconnection substrate wherein the terminals on the interconnection substrate are plated through holes.
Claim 2
Dependent Claim
251 words
A semiconductor package assembly, comprising: an interconnection substrate having a plurality of terminals; a first bare semiconductor device having a front surface and a back surface, and also comprising a plurality of terminals on the front surface; a second bare semiconductor device stacked atop the first semiconductor device having a front surface and a back surface, and also comprising a plurality of terminals on the front surface, each of the first and second bare semiconductor devices having a front surface and a back surface; the second bare semiconductor device disposed in an offset stacked manner so that the front surface of the second bare semiconductor device is adjacent the back surface of the first bare semiconductor device, and an edge portion of the second bare semiconductor device is exposed beyond an edge of the first bare semiconductor device; a first set of elongate interconnection elements extending from the terminals on the front surface of the first bare semiconductor device, said first set of elongate interconnection elements having free ends contacting a first portion of the plurality of terminals on the interconnection substrate; and a second set of elongate interconnection elements extending from the terminals on the front surface of the second bare semiconductor device, said terminals disposed in the edge portion of the second bare semiconductor device, said second set of elongate interconnection elements having free ends contacting a second portion of the plurality of terminals on the interconnection substrate wherein the terminals on the interconnection substrate are plated through holes.
Claim 3
Dependent Claim
32 words
The semiconductor package assembly, according to claim 1, wherein: the second bare semiconductor device is offset in one direction from the first bare semiconductor device so that the edge portion is rectangular.
Claim 4
Dependent Claim
32 words
The semiconductor package assembly, according to claim 1, wherein: the second bare semiconductor device is offset in two directions from the first bare semiconductor device so that the edge portion is L-shaped.
Claim 5
Dependent Claim
152 words
The semiconductor package assembly, according to claim 1, further comprising: a third additional bare semiconductor device having a front surface and a back surface; and also comprising a plurality of terminals on the front surface, the third bare semiconductor device disposed atop the second bare semiconductor device in an offset stacked manner so that the front surface of the third bare semiconductor device is adjacent the back surface of the second bare semiconductor device, and an edge portion of the third bare semiconductor device is exposed beyond an edge of the second bare semiconductor device; a third set of elongate interconnection elements extending from the terminals on the front surface of the third bare semiconductor device, said terminals disposed in the edge portion of the third bare semiconductor device, said third set of elongate interconnection elements having free ends contacting a third portion of the plurality of terminals on the interconnection substrate.
Claim 6
Dependent Claim
75 words
The semiconductor package assembly, according to claim 1, wherein the first and second bare semiconductor devices comprise a first stacked subassembly, and further comprising: a second stacked subassembly formed in the manner of the first stacked subassembly; the elongate interconnection elements of the second stacked subassembly having free ends contacting a third portion of the plurality of terminals on the interconnection substrate and a fourth portion of the plurality of terminals on the interconnection substrate.
Claim 7
Dependent Claim
63 words
The semiconductor package assembly, according to claim 5, wherein the interconnection substrate has a front surface and a back surface; and wherein: the first and second plurality of terminals on the interconnection substrate are disposed on the front surface of the interconnection substrate; and the third plurality of terminals on the interconnection substrate are disposed on the front surface of the interconnection substrate.
Claim 8
Dependent Claim
63 words
The semiconductor package assembly, according to claim 5, wherein the interconnection substrate has a front surface and a back surface; and wherein: the first and second plurality of terminals on the interconnection substrate are disposed on the front surface of the interconnection substrate; and the third plurality of terminals on the interconnection substrate are disposed on the back surface of the interconnection substrate.
Claim 9
Dependent Claim
17 words
The semiconductor package assembly, according to claim 1, wherein: the interconnection substrate is a printed circuit board.
Claim 10
Dependent Claim
15 words
The semiconductor package assembly, according to claim 1, wherein: the semiconductor devices are memory chips.
Claim 11
Dependent Claim
17 words
The semiconductor package assembly, according to claim 1, wherein: the elongate interconnection elements are resilient contact structures.
Claim 12
Dependent Claim
40 words
The semiconductor package assembly, according to claim 1, wherein: selected ones of the terminals of at least one of the first and second bare semiconductor devices are re-routed from an initial location to a desired location on the semiconductor device.
Claim 13
Dependent Claim
38 words
The semiconductor package assembly, according to claim 1, further comprising: a material selected from the group consisting of solder, braze and conductive epoxy securing the free ends of the interconnection elements to the terminals on the interconnection substrate.
Claim 14
Dependent Claim
243 words
A semiconductor package assembly, comprising: an interconnection substrate having a plurality of terminals; a first bare semiconductor die having a first surface facing the interconnection substrate and a second surface; and also comprising a plurality of terminals on the first surface; a second bare semiconductor die having a first surface facing the interconnection substrate and a second surface, and stacked atop the first semiconductor die; and also comprising a plurality of terminals on the first surface; the second bare semiconductor die disposed in an offset stacked manner so that the first surface of the second bare semiconductor die is adjacent the second surface of the first bare semiconductor die, and an edge portion of the second bare semiconductor die is exposed beyond an edge of the first bare semiconductor die; a first set of elongate interconnection elements extending from the terminals on the first surface of the first bare semiconductor die, said first set of elongate interconnection elements having free ends contacting a first portion of the plurality of terminals on the interconnection substrate; and a second set of elongate interconnection elements extending from the terminals on the first surface of the second bare semiconductor die, said terminals disposed in the edge portion of the second bare semiconductor die, said second set of elongate interconnection elements having free ends contacting a second portion of the plurality of terminals on the interconnection substrate wherein the terminals on the interconnection substrate are plated through holes.
Claim 15
Dependent Claim
243 words
A semiconductor package assembly, comprising: an interconnection substrate having a plurality of terminals; a first bare semiconductor die having a first surface facing the interconnection substrate and a second surface; and also comprising a plurality of terminals on the first surface; a second bare semiconductor die having a first surface facing the interconnection substrate and a second surface, and stacked atop the first semiconductor die; and also comprising a plurality of terminals on the first surface; the second bare semiconductor die disposed in an offset stacked manner so that the first surface of the second bare semiconductor die is adjacent the second surface of the first bare semiconductor die, and an edge portion of the second bare semiconductor die is exposed beyond an edge of the first bare semiconductor die; a first set of elongate interconnection elements extending from the terminals on the first surface of the first bare semiconductor die, said first set of elongate interconnection elements having free ends contacting a first portion of the plurality of terminals on the interconnection substrate; and a second set of elongate interconnection elements extending from the terminals on the first surface of the second bare semiconductor die, said terminals disposed in the edge portion of the second bare semiconductor die, said second set of elongate interconnection elements having free ends contacting a second portion of the plurality of terminals on the interconnection substrate wherein the terminals on the interconnection substrate are plated through holes.
Claim 16
Dependent Claim
37 words
The semiconductor package assembly, according to claim 13, wherein: the second bare semiconductor die is offset in at least one dimension so that the second bare semiconductor die extends beyond an edge of the first semiconductor die.
Claim 17
Dependent Claim
75 words
The semiconductor package assembly, according to claim 13, wherein the first and second bare semiconductor die comprise a first stacked subassembly, and further comprising: a second stacked subassembly formed in the manner of the first stacked subassembly; the elongate interconnection elements of the second stacked subassembly having free ends contacting a third portion of the plurality of terminals on the interconnection substrate and a fourth portion of the plurality of terminals on the interconnection substrate.
Claim 18
Dependent Claim
50 words
The semiconductor package assembly, according to claim 15, further comprising the interconnection substrate having a first surface and a second surface, and wherein: the first stacked subassembly is disposed on the first surface of the substrate; and the second stacked subassembly is disposed on the second surface of the substrate.
Claim 19
Dependent Claim
17 words
The semiconductor package assembly, according to claim 13, wherein: the interconnection substrate is a printed circuit board.
Claim 20
Dependent Claim
15 words
The semiconductor package assembly, according to claim 13, wherein: the semiconductor die are memory chips.
Claim 21
Dependent Claim
17 words
The semiconductor package assembly, according to claim 13, wherein: the elongate interconnection elements are resilient contact structures.
Claim 22
Dependent Claim
40 words
The semiconductor package assembly, according to claim 13, wherein: selected ones of the terminals of at least one of the first and second bare semiconductor devices are re-routed from an initial location to a desired location on the semiconductor device.
Claim 23
Dependent Claim
38 words
The semiconductor package assembly, according to claim 13, further comprising: a material selected from the group consisting of solder, braze and conductive epoxy securing the free ends of the interconnection elements to the terminals on the interconnection substrate.
Claim 24
Dependent Claim
247 words
The semiconductor package assembly, comprising: an interconnection substrate having a plurality of terminals; a first bare semiconductor die having a first surface facing the interconnection substrate and a second surface; and also comprising a plurality of terminals on the first surface; a second bare semiconductor die having a first surface facing the interconnection substrate and a second surface, and stacked atop the first semiconductor die; and also comprising a plurality of terminals on the first surface; the second bare semiconductor die disposed in an offset stacked manner so that the first surface of the second bare semiconductor die is adjacent the second surface of the first bare semiconductor die, and an edge portion of the second bare semiconductor die is exposed beyond an edge of the first bare semiconductor die; a first set of elongate interconnection elements extending from terminals on the first surface of the first bare semiconductor die, said first set of elongate interconnection elements having free ends directly in contact with a first portion of the plurality of terminals on the interconnection substrate; and a second set of elongate interconnection elements extending from terminals on the first surface of the second bare semiconductor die, said terminals disposed in the edge portion of the second bare semiconductor die, said second set of elongate interconnection elements having free ends directly in contact with a second portion of the plurality of terminals on the interconnection substrate wherein the terminals on the interconnection substrate are plated through holes.
Claim 25
Dependent Claim
247 words
The semiconductor package assembly, comprising: an interconnection substrate having a plurality of terminals; a first bare semiconductor die having a first surface facing the interconnection substrate and a second surface; and also comprising a plurality of terminals on the first surface; a second bare semiconductor die having a first surface facing the interconnection substrate and a second surface, and stacked atop the first semiconductor die; and also comprising a plurality of terminals on the first surface; the second bare semiconductor die disposed in an offset stacked manner so that the first surface of the second bare semiconductor die is adjacent the second surface of the first bare semiconductor die, and an edge portion of the second bare semiconductor die is exposed beyond an edge of the first bare semiconductor die; a first set of elongate interconnection elements extending from terminals on the first surface of the first bare semiconductor die, said first set of elongate interconnection elements having free ends directly in contact with a first portion of the plurality of terminals on the interconnection substrate; and a second set of elongate interconnection elements extending from terminals on the first surface of the second bare semiconductor die, said terminals disposed in the edge portion of the second bare semiconductor die, said second set of elongate interconnection elements having free ends directly in contact with a second portion of the plurality of terminals on the interconnection substrate wherein the terminals on the interconnection substrate are plated through holes.
Claim 26
Dependent Claim
37 words
The semiconductor package assembly, according to claim 22, wherein: the second bare semiconductor die is offset in at least one dimension so that the second bare semiconductor die extends beyond an edge of the first semiconductor die.
Claim 27
Dependent Claim
78 words
The semiconductor package assembly, according to claim 22, wherein the first and second bare semiconductor dice comprise a first stacked subassembly, and further comprising: a second stacked subassembly formed in the manner of the first stacked subassembly; the elongate interconnection elements of the second stacked subassembly having free ends directly in contact with a third portion of the plurality of terminals on the interconnection substrate and a fourth portion of the plurality of terminals on the interconnection substrate.
Claim 28
Dependent Claim
50 words
The semiconductor package assembly, according to claim 24, further comprising the interconnection substrate having a first surface and a second surface, and wherein: the first stacked subassembly is disposed on the first surface of the substrate; and the second stacked subassembly is disposed on the second surface of the substrate.
Claim 29
Dependent Claim
17 words
The semiconductor package assembly, according to claim 22, wherein: the interconnection substrate is a printed circuit board.
Claim 30
Dependent Claim
15 words
The semiconductor package assembly, according to claim 22, wherein: the semiconductor devices are memory chips.
Claim 31
Dependent Claim
17 words
The semiconductor package assembly, according to claim 22, wherein: the elongate interconnection elements are resilient contact structures.
Claim 32
Dependent Claim
40 words
The semiconductor package assembly, according to claim 22, wherein: selected ones of the terminals of at least one of the first and second bare semiconductor devices are re-routed from an initial location to a desired location on the semiconductor device.
Claim 33
Dependent Claim
38 words
The semiconductor package assembly, according to claim 22, further comprising: a material selected from the group consisting of solder, braze and conductive epoxy securing the free ends of the interconnection elements to the terminals on the interconnection substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-06 | 2003-06-07 | 2003-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-06 | 2007-06-07 | 2007-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-06 | 2011-06-07 | 2011-12-07 | $7700.00 | Window Closed / Lapsed |