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US5212406A Expired / Lapsed US ⏱️ 0.0 years remaining

High density packaging of solid state devices

Assignee: Eastman Kodak Co
•
Filing: 1992-01-06
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Granted: 1993-05-18
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Expires: 2012-01-06
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Abstract

Abstract An assembly of multiple quantities of solid state memory modules, built upon a high density interconnect substrate, is described. Each memory module is of itself constructed from a multiple number of separate bare solid state memory die appropriate to the function. A multiplicity of the memory modules are constructed on a single substrate, and thereupon each module is separated from the single substrate. The separate memory die are mounted to the surface of the high density substrate, which provides the interconnection necessary to complete the memory function. The high density substrate also provides the capability for close attached capacitors for signal filtering, test vias for optimal module test and thermal vias as appropriate. The provision for multiple memory modules enables economical manufacturing plus capability for systems level interconnect.

Inventors

  • 👤 Samuel Reele
  • 👤 Thomas R. Pian

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 23:38
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10W; H10W44/00; H10W44/601; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W90/00

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 108 words
An array of electronic packaging substrates that is useable for testing, the array comprising: a support means for supporting a plurality of testable modules; a plurality of semiconductor chips mounted on a front surface of said support means, said chips being divided into subsets of chips, each subset being part of a different testable module and including a plural number of chips; a passive circuit element located beneath a chip of each testable module; a plurality of test pads located on a back surface of said support means; and a conductive via coupling one of said test pads to leads on the front surface of said support means.
Claim 2
Dependent Claim 108 words
An array of electronic packaging substrates that is useable for testing, the array comprising: a support means for supporting a plurality of testable modules; a plurality of semiconductor chips mounted on a front surface of said support means, said chips being divided into subsets of chips, each subset being part of a different testable module and including a plural number of chips; a passive circuit element located beneath a chip of each testable module; a plurality of test pads located on a back surface of said support means; and a conductive via coupling one of said test pads to leads on the front surface of said support means.
Claim 3
Dependent Claim 14 words
The array of claim 1 and wherein the passive circuit element is a capacitor.
Claim 4
Dependent Claim 12 words
The array of claim 1 and wherein the chips are memory chips.
Claim 5
Dependent Claim 24 words
The array of claim 3 and wherein the memory chips are mounted to the front surface of said support means in a flip-chip arrangement.
Claim 6
Dependent Claim 14 words
The array of claim 3 and wherein the passive circuit element is a capacitor.
Claim 7
Dependent Claim 17 words
The array of claim 1 and wherein each testable module comprises four flash EEPROM type memory chips.
Claim 8
Dependent Claim 16 words
The array of claim 1 and wherein each testable module comprises eight SRAM type memory chips.
Claim 9
Dependent Claim 15 words
The array of claim 1 and wherein each testable module is surrounded by scoring lines.
Claim 10
Dependent Claim 20 words
The array of claim 3 and wherein the test pads are beneath at least one memory chip of each module.
Claim 11
Dependent Claim 12 words
The array of claim 8 and wherein the chips are memory chips.
Claim 12
Dependent Claim 17 words
The array of claim 10 and wherein each testable module comprises four flash EEPROM type memory chips.

References Cited (Backward Citations)

US4426773A Cited
US4578697A Cited
US4419530A Cited
US4701781A Cited
US4801561A Cited
US4742385A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-05-17 1996-11-16 1997-05-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-05-17 2000-11-16 2001-05-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-05-17 2004-11-16 2005-05-18 $7700.00 Window Closed / Lapsed

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