US5373189A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three-dimensional multichip module
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
•
Filing: 1993-07-30
•
Granted: 1994-12-13
•
Expires: 2013-07-30
Abstract
Abstract Three-dimensional multichip module. The invention relates to a three-dimensional or 3D multichip module having a plurality of bidimensional, elementary electronic modules (4a-4d), each incorporating at least one chip (10a-10d), a support (6a-6d) on which is placed the chip and a conductive interconnection network or array (8a-8d) covering an upper surface of the support. These elementary modules are substantially superimposed in a displaced manner (in the form of a staircase) and are interconnected by means of their interconnection networks and connection pads (12a-12d) placed on those parts of the elementary modules not covered by the upper elementary module. Application to the association of integrated circuits in microconnection technology.
Inventors
- 👤 Claude Massit
- 👤 Gerard Nicolas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:55
CPC Classifications
H; H10; H10W; H10W90/00; H10W70/00; H10W70/60; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W90/20; H10W90/22; H10W90/24; H10W90/291; H10W90/701; H10W90/721; H10W90/724; H10W90/751; H10W90/752
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
124 words
Multichip module having a substrate (2) and plurality of bidimensional, elementary electronic modules (4a-4d), each having at least one chip (10-10d) and a support (6a-6d) on which is placed the chip, the elementary modules being substantially superimposed and deposited on the substrate, characterized in that the substrate and the supports of the elementary modules have in each case an upper face covered by an interconnection network and in that the elementary modules which are substantially superimposed are displaced with respect to one another and with respect to the substrate in such a way that a portion of each interconnection network is not covered by the support of an upper elementary module, so as to permit the interconnection of the interconnection networks by electric wires.
Claim 2
Dependent Claim
124 words
Multichip module having a substrate (2) and plurality of bidimensional, elementary electronic modules (4a-4d), each having at least one chip (10-10d) and a support (6a-6d) on which is placed the chip, the elementary modules being substantially superimposed and deposited on the substrate, characterized in that the substrate and the supports of the elementary modules have in each case an upper face covered by an interconnection network and in that the elementary modules which are substantially superimposed are displaced with respect to one another and with respect to the substrate in such a way that a portion of each interconnection network is not covered by the support of an upper elementary module, so as to permit the interconnection of the interconnection networks by electric wires.
Claim 3
Dependent Claim
49 words
Multichip module according to claim 1, characterized in that, on a lower face, the supports have a cavity (14a-14d) with a size significantly greater than that of the chips, so that the support of a first elementary module can be placed above the chip of a second elementary module.
Claim 4
Dependent Claim
64 words
Multichip module according to claim 1, characterized in that each elementary module has at least one connecting pad (12a-12d) placed on one edge of the support and connected to the chip by means of the interconnection network, each connecting pad being connected to the connecting pads of the upper and lower elementary modules in order to ensure an electrical connection between said elementary modules.
Claim 5
Dependent Claim
27 words
Multichip module according to claim 1, characterized in that each elementary module has a plurality of chips connected to one another by means of the interconnection network.
References Cited (Backward Citations)
WO1988005251A1
Cited
US4956694A
Cited
US5019943A
Cited
US5311401A
Cited
US5128831A
Cited
US5313096A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |