US5996091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CPLD serial programming with extra read register
Assignee: Intellectual Ventures II LLC
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Filing: 1997-08-19
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Granted: 1999-11-30
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Expires: 2017-08-19
Abstract
Abstract A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally. The novel method further comprises instructing the CPLD to program again, or overprogram, the program data into the memory location if the program data matches the verify data. The novel method further comprises reprogramming the program data into the memory location if the program data does not match the verify data.
Inventors
- 👤 Christopher W. Jones
- 👤 David L. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:12
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G11; G11C; G11C29/00; G11C29/52
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
75 words
A method comprising: loading into an integrated circuit device in response to a single, first instruction program data into a first data storage element and address information into an address storage element and programming in response to said first instruction said program data into a memory location having an address defined by said address information; and verifying successful programming of said integrated circuit using said program data as a verification mask within said integrated circuit.
Claim 2
Independent Claim
75 words
A method comprising: loading into an integrated circuit device in response to a single, first instruction program data into a first data storage element and address information into an address storage element and programming in response to said first instruction said program data into a memory location having an address defined by said address information; and verifying successful programming of said integrated circuit using said program data as a verification mask within said integrated circuit.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said verifying comprises comparing verify data read from said memory location in response to a second instruction with said program data.
Claim 4
Dependent Claim
19 words
The method of claim 2 further comprising the step of: outputting said verify data from said integrated circuit device.
Claim 5
Dependent Claim
18 words
The method of claim 3, wherein outputting comprises serially outputting said verify data from said integrated circuit device.
Claim 6
Dependent Claim
25 words
The method of claim 2, further comprising the step of: programming again in response to a programming instruction said program data into said memory location.
Claim 7
Dependent Claim
31 words
The method of claim 5, wherein if said program data matches said verify data then: updating said address information or said program data; and repeating said loading, programming and verifying operations.
Claim 8
Dependent Claim
12 words
The method of claim 6, further comprising repeating said programming again operation.
Claim 9
Dependent Claim
38 words
The method of claim 5, wherein if said program data does not match said verify data then: repeating said programming and verifying operations for a predetermined number of times or until said verify data matches said program data.
Claim 10
Dependent Claim
13 words
The method of claim 5, wherein said programming instruction requires Z clock cycles.
Claim 11
Dependent Claim
30 words
The method of claim 1, wherein loading comprises serially shifting said program data into said first data storage element, and serially shifting said address information into said address storage element.
Claim 12
Dependent Claim
15 words
The method of claim 1, wherein said integrated circuit device comprises a programmable logic device.
Claim 13
Dependent Claim
24 words
The method of claim 1, wherein: said first data storage element comprises a first register; and said address storage element comprises a second register.
Claim 14
Independent Claim
123 words
A method for programming an integrated circuit device comprising: instructing in a first instructing step said integrated circuit device in one instruction to load program data, load address information and program said program data into a memory location having an address defined by said address information; loading said program data into a first data storage element and said address information into an address storage element, wherein said program data passes through said address storage element into said first data storage element; programming in a first programming step said program data into said memory location; instructing in a second instructing step said integrated circuit device to read verify data from said memory location; and capturing said verify data into a second data storage element.
Claim 15
Independent Claim
123 words
A method for programming an integrated circuit device comprising: instructing in a first instructing step said integrated circuit device in one instruction to load program data, load address information and program said program data into a memory location having an address defined by said address information; loading said program data into a first data storage element and said address information into an address storage element, wherein said program data passes through said address storage element into said first data storage element; programming in a first programming step said program data into said memory location; instructing in a second instructing step said integrated circuit device to read verify data from said memory location; and capturing said verify data into a second data storage element.
Claim 16
Independent Claim
123 words
A method for programming an integrated circuit device comprising: instructing in a first instructing step said integrated circuit device in one instruction to load program data, load address information and program said program data into a memory location having an address defined by said address information; loading said program data into a first data storage element in said address information into an address storage element; programming in a first programming step said program data into said memory location; instructing in a second instructing step said integrated circuit device in one instruction to read data from said memory location and to program again said program data into said memory location; and capturing said data from said memory location into a second data storage element.
Claim 17
Independent Claim
123 words
A method for programming an integrated circuit device comprising: instructing in a first instructing step said integrated circuit device in one instruction to load program data, load address information and program said program data into a memory location having an address defined by said address information; loading said program data into a first data storage element in said address information into an address storage element; programming in a first programming step said program data into said memory location; instructing in a second instructing step said integrated circuit device in one instruction to read data from said memory location and to program again said program data into said memory location; and capturing said data from said memory location into a second data storage element.
Claim 18
Dependent Claim
18 words
The method of claim 14, further comprising the step of: comparing said verify data with said program data.
Claim 19
Dependent Claim
24 words
The method of claim 15, wherein said comparing step further comprises comparing said verify data and said program data within said integrated circuit device.
Claim 20
Dependent Claim
18 words
The method of claim 16, wherein said comparing step further comprises using said program data as a mask.
Claim 21
Dependent Claim
34 words
The method of claim 14, further comprising the steps of: outputting said verify data from said integrated circuit device; and comparing said verify data and said program data externally to said integrated circuit device.
Claim 22
Dependent Claim
21 words
The method of claim 18, wherein said outputting step further comprises serially outputting said verify data from said integrated circuit device.
Claim 23
Dependent Claim
24 words
The method of claim 15, further comprising the step of: programming again in a second programming step said program data into said memory location.
Claim 24
Dependent Claim
57 words
The method of claim 20, wherein if said program data matches said verify data said method further comprises the steps of: updating said address information or said program data; and repeating said first instructing step, said loading step, said first programming step, said second instructing step, said capturing step, said comparing step and said second programming step.
Claim 25
Dependent Claim
50 words
The method of claim 20, wherein if said program data does not match said verify data said method further comprises the step of: repeating said capturing step, said comparing step and said second programming step for a predetermined number of times or until said verify data matches said program data.
Claim 26
Independent Claim
125 words
A method for programming an integrated circuit device comprising: instructing in a first instructing step requiring Z clock cycles said integrated circuit device in one instruction to load program data, load address information and program said program data into a memory location having an address defined by said address information; loading in X clock cycles said program data into a first data storage element and in Y clock cycles said address information into an address storage element; programming in a first programming step said program data into said memory location; instructing in a second instructing step requiring Z clock cycles said integrated circuit device to read data from said memory location; and capturing said data from said memory location into a second data storage element.
Claim 27
Independent Claim
125 words
A method for programming an integrated circuit device comprising: instructing in a first instructing step requiring Z clock cycles said integrated circuit device in one instruction to load program data, load address information and program said program data into a memory location having an address defined by said address information; loading in X clock cycles said program data into a first data storage element and in Y clock cycles said address information into an address storage element; programming in a first programming step said program data into said memory location; instructing in a second instructing step requiring Z clock cycles said integrated circuit device to read data from said memory location; and capturing said data from said memory location into a second data storage element.
References Cited (Backward Citations)
US3831148A
Cited
US4734852A
Cited
US4860293A
Cited
US4910664A
Cited
US4929889A
Cited
US5103450A
Cited
US5142223A
Cited
US5258986A
Cited
US5195097A
Cited
US5396170A
Cited
US5412260A
Cited
US5301156A
Cited
US5311520A
Cited
US5404526A
Cited
US5381419A
Cited
US5444716A
Cited
US5608885A
Cited
US5557619A
Cited
US5574879A
Cited
US5574684A
Cited
US5519715A
Cited
US5805794A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |