US5258986A
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Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
Assignee: NXP BV
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Filing: 1990-09-19
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Granted: 1993-11-02
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Expires: 2010-09-19
Abstract
Abstract RAM Built-In Self-Test logic is presented that utilizes a linear feedback shift register (LFSR) to generate data. Preferably, an LFSR is also utilized for address generation during memory self-testing. More than one cycle is implemented with offset of successive data sequences relative to address sequences to increase fault coverage. Memory storage is utilized in the data generation to enable a reduced area of the data generation circuitry.
Inventors
- 👤 Jared L. Zerbe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/36; G11C29/10; G11C29/18; G11C29/20
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
180 words
A method of testing memory having a set of M memory locations, said method comprising the steps of: (a) generating a first sequence F k that is pseudorandom; (b) generating a second sequence S k ; one of said first and second sequences is utilized as an address sequence A k and the other of said first and second sequences is utilized as a data sequence D k ; (c) for k=1 to some integer N, storing a kth data word D k in a memory location at address A k ; (d) for a sequence of values of k=1 to some integer L, comparing a value of data actually stored in the memory location at address A k with a value of the data word D k that was to be stored there to determine if there has been an error in storing this data word in this memory location; (e) generating a third sequence T k that is pseudorandom; and repeating steps (c) and (d) with third sequence T k in place of first sequence F k .
Claim 2
Independent Claim
180 words
A method of testing memory having a set of M memory locations, said method comprising the steps of: (a) generating a first sequence F k that is pseudorandom; (b) generating a second sequence S k ; one of said first and second sequences is utilized as an address sequence A k and the other of said first and second sequences is utilized as a data sequence D k ; (c) for k=1 to some integer N, storing a kth data word D k in a memory location at address A k ; (d) for a sequence of values of k=1 to some integer L, comparing a value of data actually stored in the memory location at address A k with a value of the data word D k that was to be stored there to determine if there has been an error in storing this data word in this memory location; (e) generating a third sequence T k that is pseudorandom; and repeating steps (c) and (d) with third sequence T k in place of first sequence F k .
Claim 3
Dependent Claim
41 words
A method as in claim 1 wherein N equals M and each of the N data words D k is stored in a uniquely associated address A k , so that every memory location has data stored therein by step (c).
Claim 4
Dependent Claim
37 words
A method as in claim 1 wherein T k =F r where r=(k+q) Mod M for some integer q, whereby the third sequence T k is just an offset version of the first sequence F k :
Claim 5
Dependent Claim
23 words
A method as in claim 1 wherein step (b) comprises the step of generating the second sequence S k with an m-bit counter.
Claim 6
Dependent Claim
22 words
A method as in claim 1 wherein step (a) comprises generating the first sequence F k with a linear feedback shift register.
Claim 7
Dependent Claim
22 words
A method as in claim 5 wherein step (e) comprises generating the third sequence T k with a linear feedback shift register.
Claim 8
Dependent Claim
22 words
A method as in claim 6 wherein the same linear feedback shift register is utilized to generate the first and third sequences.
Claim 9
Dependent Claim
16 words
A method as in claim 7 wherein the first and third sequences are utilized as addresses.
Claim 10
Dependent Claim
19 words
A method as in claim 8 wherein said linear feedback shift register also generates addresses utilized in step (d).
Claim 11
Dependent Claim
41 words
A method as in claim 9 wherein L is equal to M-q, for some integer q, and wherein said linear feedback shift register repeatedly generates the same sequence of addresses so that T k =F r , where r=k-q mod M.
Claim 12
Dependent Claim
42 words
A method as in claim 10 wherein N=M, wherein q=1 and wherein said linear feedback shift register generates a set of M=2 m addresses, for some integer m, in step (a) and (e) and generates 2 m -1 addresses in step (d).
Claim 13
Dependent Claim
25 words
A method as in claim 5 wherein step (b) comprises the step of generating the third sequence T k with a linear feedback shift register.
Claim 14
Dependent Claim
22 words
A method as in claim 12 wherein the same linear feedback shift register is utilized to generate the first and second sequences.
Claim 15
Dependent Claim
47 words
A method as in claim 13 wherein a first subset of a set of Q output lines from said linear feedback shift register provide said address A k and a subset of P output lines from said linear feedback shift register provide said data D k .
Claim 16
Dependent Claim
42 words
A method as in claim 1 wherein the sequence that is utilized as the data sequence is generated by a linear feedback shift register that utilizes a memory data register of said memory as storage elements of the linear feedback shift register.
Claim 17
Dependent Claim
24 words
A method as in claim 1 wherein step (d) utilizes a core of said memory as a source of a next state data element.
Claim 18
Dependent Claim
149 words
A memory having built-in self-test logic, said memory comprising: a memory core having M memory locations; means for generating a first sequence F k that is pseudorandom, a second sequence S k and a third sequence T k that is pseudorandom; one of the first and second sequences functions as an address sequence A k and the other functions as a data sequence D k ; means, for each value of k=1, . . . , M, for storing the kth data element D k in a location in said memory core at address A k determined from the first and second sequences and also for storing the kth data element D k in a location in said memory core at address A k determined from said second and third sequences; and means for comparing expected values in said memory core with actual values stored in this memory core.
Claim 19
Dependent Claim
149 words
A memory having built-in self-test logic, said memory comprising: a memory core having M memory locations; means for generating a first sequence F k that is pseudorandom, a second sequence S k and a third sequence T k that is pseudorandom; one of the first and second sequences functions as an address sequence A k and the other functions as a data sequence D k ; means, for each value of k=1, . . . , M, for storing the kth data element D k in a location in said memory core at address A k determined from the first and second sequences and also for storing the kth data element D k in a location in said memory core at address A k determined from said second and third sequences; and means for comparing expected values in said memory core with actual values stored in this memory core.
Claim 20
Dependent Claim
20 words
A memory as in claim 17 wherein T k equals F r where r=k-q mod M for some integer q.
Claim 21
Dependent Claim
25 words
A memory as in claim 17 wherein said means for generating the first, second and third sequences includes a counter for generating the second sequence.
Claim 22
Dependent Claim
27 words
A memory as in claim 17 wherein said means for generating the first, second and third sequences includes a linear feedback shift register for generating pseudorandom sequences.
Claim 23
Dependent Claim
19 words
A memory as in claim 20 wherein said linear feedback shift register generates both the first and third sequences.
Claim 24
Dependent Claim
16 words
A memory as in claim 21 wherein said first and third sequences are utilized as addresses.
Claim 25
Dependent Claim
21 words
A memory as in claim 22 wherein said linear feedback shift register also generates addresses utilized by said means for comparing.
Claim 26
Dependent Claim
29 words
A memory as in claim 23 wherein said linear feedback shift register further comprises means for altering a length of pseudorandom sequence produced by this linear feedback shift register.
Claim 27
Dependent Claim
28 words
A memory as in claim 24 wherein said linear feedback shift register can produce sequences of length 2 m and length 2 m -1 for some integer m.
Claim 28
Dependent Claim
10 words
A memory as in claim 25 wherein M=2 m .
Claim 29
Dependent Claim
42 words
A memory as in claim 20 wherein said addresses are produced on a set of Q output lines of said linear feedback shift register and said data is produced on a set of P output lines of said linear feedback shift register.
Claim 30
Dependent Claim
30 words
A memory as in claim 20 wherein said linear feedback shift register utilizes a memory data register of said core memory as storage elements of this linear feedback shift register.
Claim 31
Dependent Claim
34 words
A memory as in claim 20 wherein said core memory is a dual port core memory and wherein said linear feedback shift register is formed from memory elements within said core and additional logic.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-01 | 1997-05-03 | 1997-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-01 | 2001-05-03 | 2001-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-01 | 2005-05-03 | 2005-11-02 | $7700.00 | Window Closed / Lapsed |