High speed tester

Claim 2

A data processing apparatus comprising: memory means for storing and supplying data signals and codes; cache means for storing a predetermined set of the data signals; at least first and second shift registers connected to the memory means and the cache means, the shift registers operative to selectively receive the data signals and operative to shift the stored data signals onto first and second output lines at a predetermined clock cycle rate in response to first and second clock pulses, the second clock pulses being delayed with respect to the first clock pulses; control means for providing operational control to the apparatus, the control means responsive to the data signals and codes stored in the memory means for controlling shift register data signals input from the memory means and the cache means, and further for controlling the storing of a predetermined set of data signals in the cache means; and an output multiplexer connected to receive the data signals on the first and second output lines and operative to provide an output having recurrent groups of signals from the first and second registers.

Claim 3

The apparatus of claim 1 wherein the data signals are test data signals comprising addresses, commands, and data.

Claim 4

The apparatus of claim 1 further comprising storage address register means for applying address signals to the memory means and for saving the first address plus one of a test loop.

Claim 5

The apparatus of claim 3 further comprising control processor means for supplying external commands and addresses to the control means and storage address register means.

Claim 6

The apparatus of claim 4 further comprising data multiplexer means for routing data signals to the shift registers in response to control means signals.

Claim 7

The apparatus of claim 5 wherein the storage address register (SAR) means comprises: a SAR counter; SAR register means for loading the SAR counter; and SAR mux means for routing address input to the SAR register.

Claim 8

The apparatus of claim 6 wherein addresses are loaded into the SAR register from the SAR counter and the control processor through the SAR mux means.

Claim 9

The apparatus of claim 7 wherein the predetermined set of data signals correspond to the first and last addresses of a loop of data signals.

Claim 10

The apparatus of claim 8 wherein each of the shift registers has "n" positions and wherein the control means control applying the data signals to the shift registers from the memory means and the cache means such that the effective memory access time is equal to "n" multiplied by the clock cycle rate and the apparatus output provides two bits of digital data for each clock cycle.

Claim 11

The apparatus of claim 9 wherein the control means comprises: means for decoding the codes; input latches responsive to commands from the control processor; shift register controller means for controlling apparatus timing; and a plurality of latches responsive to outputs of the input latches, clock signals, and the output of the shift register controller, the plurality of latches operative to generate apparatus control timing pulses.

Claim 12

The apparatus of claim 4 wherein the control means comprises: means for decoding the codes; input latches responsive to commands from the control processor; shift register controller means for controlling apparatus timing; and a plurality of latches responsive to the outputs of the input latches, clock signals, and the output of the shift register controller, the plurality of latches operative to generate apparatus control timing pulses.

Claim 13

A test apparatus for testing a multiple input pin device under test comprising a multiplicity of apparatuses defined in claim 1, each apparatus being coupled to a respective input pin.

Claim 14

A high speed tester comprising: memory means for addressably storing and supplying test data signals and codes; cache means for addressably storing a predetermined set of the test data signals; storage address register means for applying address signals to the memory means and for saving the first address plus one of a test loop; at least first and second shift registers each having "n" positions connected to the memory means and the cache means, the shift registers operative to selectively receive the test data signals and operative to shift the stored data signals onto first and second output lines at a predetermined clock cycle rate in response to first and second clock pulses, the second clock pulses being delayed with respect to the first clock pulses; control means for providing operational control to the tester, the control means responsive to the data signals and codes stored in the memory means for controlling shift register test data signals input from the memory means and the cache means, and further for controlling the storing of a predetermined set of test data signals in the cache means, wherein the control means controls applying the test data to the shift registers connected to the memory means and the cache means such that the effective memory access time is equal to "n" multiplied by the clock cycle rate and the tester provides two bits of digital data for each clock cycle; and an output multiplexer connected to receive the test data signals on the first and second output lines and operative to provide an output having recurrent groups of signals from the first and second registers.

Claim 15

A high speed tester comprising: memory means for addressably storing and supplying test data signals and codes; cache means for addressably storing a predetermined set of the test data signals; storage address register means for applying address signals to the memory means and for saving the first address plus one of a test loop; at least first and second shift registers each having "n" positions connected to the memory means and the cache means, the shift registers operative to selectively receive the test data signals and operative to shift the stored data signals onto first and second output lines at a predetermined clock cycle rate in response to first and second clock pulses, the second clock pulses being delayed with respect to the first clock pulses; control means for providing operational control to the tester, the control means responsive to the data signals and codes stored in the memory means for controlling shift register test data signals input from the memory means and the cache means, and further for controlling the storing of a predetermined set of test data signals in the cache means, wherein the control means controls applying the test data to the shift registers connected to the memory means and the cache means such that the effective memory access time is equal to "n" multiplied by the clock cycle rate and the tester provides two bits of digital data for each clock cycle; and an output multiplexer connected to receive the test data signals on the first and second output lines and operative to provide an output having recurrent groups of signals from the first and second registers.

Claim 16

The tester of claim 13 wherein the test data signals comprise addresses, commands, and data.

Claim 17

The tester of claim 13 further comprising data multiplexer means for routing test data signals to the shift registers in response to control means signals.

Claim 18

The tester of claim 13 further comprising control processor means for supplying external commands and addresses to the control means and storage address register means.

Claim 19

The tester of claim 16 wherein the storage address register (SAR) means comprises: a SAR counter; SAR register means for loading the SAR counter; and SAR mux means for routing address input to the SAR register.

Claim 20

The apparatus of claim 17 wherein addresses are loaded into the SAR register from the SAR counter and the control processor through the SAR mux means.

Claim 21

The tester of claim 18 wherein the predetermined set of test data signals correspond to the first and last addresses of the loop of test data signals.

Claim 22

The tester of claim 19 wherein the control means comprises: means for decoding the codes; input latches responsive to signals from the control processor; shift register controller means for controlling apparatus timing; and a plurality of latches responsive to outputs of the input latches, clock signals, and the output of the shift register controller, the plurality of latches operative to generate tester control timing pulses.

Claim 23

The tester of claim 13 wherein the control means comprises: means for decoding the codes; input latches responsive to signals to the control processor; shift register controller means for controlling apparatus timing; and a plurality of latches responsive to outputs of the input latches, clock signals, and the output of the shift register controller, the plurality of latches operative to generate tester control timing pulses.

Claim 24

A test apparatus for testing a multiple input pin device under test comprising a multiplicity of apparatuses as defined in claim 13, each apparatus being coupled to a respective input pin.

Claim 25

A high speed tester for repetitively introducing loops of addressed data to a device under test comprising: control processor means for supplying external commands and addresses; address cache means for storing test data signals corresponding to the first and last addresses of each test loop; storage address register means for applying address signals to the memory means and for saving the first address plus one of each test loop; at least first and second shift registers each having "n" positions connected to the memory means and the address caches, the shift registers operative to selectively receive the test data signals and operative to serially shift the stored data signals onto first and second output lines at a predetermined clock cycle rate in response to first and second clock pulses, the second clock pulses being delayed with respect to the first clock pulses; data multiplexer means for routing test data signals to the shift registers; control means for controlling tester operation in response to external commands from the control processor, the control means further being responsive to the test data signals and codes stored in the memory means for controlling shift register test data signals input from the memory means and cache means, and still further for controlling storage of the first and last addresses of each test loop in the cache means, wherein the test data corresponding to the first and last addresses is routed from the cache means and the data corresponding to other addresses is routed from the memory means, such that the effective memory access time is equal to "n" multiplied by the clock cycle rate and the apparatus output provides two bits of digital data for each clock cycle; and an output multiplexer connected to receive the test data signals on the first and second output lines and operative to provide an output having recurrent groups of signal from the first and second registers.

Claim 26

A high speed tester for repetitively introducing loops of addressed data to a device under test comprising: control processor means for supplying external commands and addresses; address cache means for storing test data signals corresponding to the first and last addresses of each test loop; storage address register means for applying address signals to the memory means and for saving the first address plus one of each test loop; at least first and second shift registers each having "n" positions connected to the memory means and the address caches, the shift registers operative to selectively receive the test data signals and operative to serially shift the stored data signals onto first and second output lines at a predetermined clock cycle rate in response to first and second clock pulses, the second clock pulses being delayed with respect to the first clock pulses; data multiplexer means for routing test data signals to the shift registers; control means for controlling tester operation in response to external commands from the control processor, the control means further being responsive to the test data signals and codes stored in the memory means for controlling shift register test data signals input from the memory means and cache means, and still further for controlling storage of the first and last addresses of each test loop in the cache means, wherein the test data corresponding to the first and last addresses is routed from the cache means and the data corresponding to other addresses is routed from the memory means, such that the effective memory access time is equal to "n" multiplied by the clock cycle rate and the apparatus output provides two bits of digital data for each clock cycle; and an output multiplexer connected to receive the test data signals on the first and second output lines and operative to provide an output having recurrent groups of signal from the first and second registers.

Claim 27

The tester of claim 23 wherein the storage address register (SAR) means comprises: a SAR counter; SAR register means for loading the SAR counter; and SAR mux means for routing address input to the SAR register.

Claim 28

The apparatus of claim 24 wherein addresses are loaded into the SAR register from the SAR counter and the control processor through the SAR mux means.

Claim 29

The tester of claim 23 wherein the control means comprises: means for decoding the codes; input latches responsive to signals from the control processor; shift register controller means for controlling apparatus timing; and a plurality of latches responsive to the outputs of the input latches, clock signals, and the output of the shift register controller, the plurality of latches operative to generate tester control timing pulses.

Claim 30

A test apparatus for testing a multiple input pin device under test comprising a multiplicity of apparatuses as defined in claim 23, each apparatus being coupled to a respective input pin.

Claim 33

The method of claim 28 further comprising the steps of applying address signals to the memory from a storage address register and saving the first address plus one of the loop in the storage address register.

Claim 34

The method of claim 29 wherein the predetermined set of data signals corresponds to the first and last addresses of the loop.

Claim 35

The method of claim 30 further comprising the step of supplying external commands addresses and data.

Claim 36

The method of claim 31 wherein the shift registers each have "n" positions and wherein controlling the input of data signals to the shift registers from the memory and the cache yields an effective memory access time equal to "n" multiplied by the clock cycle rate.

Claim 37

The method of claim 32 wherein the step of supplying commands comprises: decoding the codes; latching the external commands in input latches; controlling the timing of the process with a shift register controller; and generating timing pulses with a plurality of latches responsive to outputs of the input latches, the clock signals, and the shift register controller output.

Claim 40

The method of claim 34 wherein the step of supplying commands comprises: decoding the codes; latching the external commands in input latches; controlling the timing of the process with a shift register controller; and generating timing pulses with a plurality of latches responsive to outputs of the input latches, the clock signals, and the shift register controller output.

Claim 41

The method of claim 35 wherein the selectively receiving step comprises receiving the test data signals corresponding to the first and last addresses from the cache and receiving the test data signals corresponding to other addresses from the memory.