Method and apparatus for detecting retention faults in memories

Claim 1

A method for fault testing each of a plurality of self-testing read and write memory elements arranged in banks, each memory element operative to execute first, second and third sequences of read and/or write operations, comprising the steps of: signaling each of the banks in succession for a first time to cause each memory element in a successive bank to execute its first sequence of read and write operations without any delay between operations, the first sequence containing a write operation which, when executed, causes a first pattern of bits to be present in that memory element at the completion of the first sequence of operations; signaling the banks of memory elements in succession for a second time, after a first predetermined interval following signaling for the first time, to cause each memory element in a successive bank to execute its second sequence of read and write operations without any delay between operations, the second sequence including a read operation which is executed by each memory at the beginning of the second sequence to read itself to determine if the first pattern of bits is present, and a write operation, which upon execution, causes a second pattern of bits, complementary to the first pattern, to be present in the memory element at the completion of the second sequence of operations; and signaling the banks of memory elements in succession for a third time., after a second predetermined interval following signaling for the second time, to cause each memory element in a successive bank to execute the third sequence of operations without any delay between operations, the third sequence including a read operation which is executed by each memory element to determine if the second pattern of bits is present therein.

Claim 2

A method for fault testing each of a plurality of self-testing read and write memory elements arranged in banks, each memory element operative to execute first, second and third sequences of read and/or write operations, comprising the steps of: signaling each of the banks in succession for a first time to cause each memory element in a successive bank to execute its first sequence of read and write operations without any delay between operations, the first sequence containing a write operation which, when executed, causes a first pattern of bits to be present in that memory element at the completion of the first sequence of operations; signaling the banks of memory elements in succession for a second time, after a first predetermined interval following signaling for the first time, to cause each memory element in a successive bank to execute its second sequence of read and write operations without any delay between operations, the second sequence including a read operation which is executed by each memory at the beginning of the second sequence to read itself to determine if the first pattern of bits is present, and a write operation, which upon execution, causes a second pattern of bits, complementary to the first pattern, to be present in the memory element at the completion of the second sequence of operations; and signaling the banks of memory elements in succession for a third time., after a second predetermined interval following signaling for the second time, to cause each memory element in a successive bank to execute the third sequence of operations without any delay between operations, the third sequence including a read operation which is executed by each memory element to determine if the second pattern of bits is present therein.

Claim 6

A method for fault testing at least one self-testing non-read/write memory element and each of a plurality of self-testing read and write memory elements arranged in banks, each read and write memory element in each bank containing first, second and third sequences of read and/or write operations, comprising the steps of: signaling each of the banks of read and write memory elements in succession for a first time to cause each memory read and write element in a successive bank to execute the first sequence of mad and write operations without any delay between operations, the first sequence containing a write operation, which, when executed, causes a first pattern of bits to be present in the read and write memory element at the completion of the first sequence of operations; signaling the non-mad and write memory element to commence self-testing after the banks of mad and write memory elements have been successively signaled; signaling the banks of mad and write memory elements in succession for a second time, after a first predetermined interval following signaling of the banks of read and write memory elements for the first time, to cause each read and write memory element in a successive bank to execute the second sequence to read and write operations without any delay between operations, the second sequence including a mad operation which is executed to read the read and write memory element to determine if the first pattern of bits is present, and a write operation, which upon execution, causes a second pattern of bits, complementary to the first pattern, to be present in the read and write memory element at the completion of the second sequence of operations; and signaling the banks of read and write memory elements in succession for a third time, after a second predetermined interval following signaling for the second time, to cause each read and write memory element in a successive bank to execute the third sequence of operations without any delay between operations, the third sequence including a read operation which is executed to determine if the second pattern of bits is present in the read and write memory element.

Claim 7

A method for fault testing at least one self-testing non-read/write memory element and each of a plurality of self-testing read and write memory elements arranged in banks, each read and write memory element in each bank containing first, second and third sequences of read and/or write operations, comprising the steps of: signaling each of the banks of read and write memory elements in succession for a first time to cause each memory read and write element in a successive bank to execute the first sequence of mad and write operations without any delay between operations, the first sequence containing a write operation, which, when executed, causes a first pattern of bits to be present in the read and write memory element at the completion of the first sequence of operations; signaling the non-mad and write memory element to commence self-testing after the banks of mad and write memory elements have been successively signaled; signaling the banks of mad and write memory elements in succession for a second time, after a first predetermined interval following signaling of the banks of read and write memory elements for the first time, to cause each read and write memory element in a successive bank to execute the second sequence to read and write operations without any delay between operations, the second sequence including a mad operation which is executed to read the read and write memory element to determine if the first pattern of bits is present, and a write operation, which upon execution, causes a second pattern of bits, complementary to the first pattern, to be present in the read and write memory element at the completion of the second sequence of operations; and signaling the banks of read and write memory elements in succession for a third time, after a second predetermined interval following signaling for the second time, to cause each read and write memory element in a successive bank to execute the third sequence of operations without any delay between operations, the third sequence including a read operation which is executed to determine if the second pattern of bits is present in the read and write memory element.