Method and apparatus for integrity testing of fault monitoring logic

Abstract

Abstract In a data processing system, a data processing unit contains data processing logic including shadowed functional registers for storing the data being processed. The units also include fault monitoring logic, including, for each shadowed functional register, a shadowing copy register connected in parallel from the corresponding shadowed register to receive and store a copy of the data resident in the shadowed register. Test logic is connected from the shadowed and shadowing registers for comparing the data resident in the shadowed and shadowing registers and providing indications of possible faults in the data processing logic. The shadowed and shadowing registers are connected in a serial scan chain through a serial scan data path. The integrity of the fault monitoring logic is tested by serially shifting, or scanning, known test patterns of bits through the serial scan chain comprised of the shadowed registers and shadowing registers. A first set of patterns are selected so that the test patterns themselves should not induce any errors to appear to the comparison logic so long as the the test logic is correct, so that any errors that are detected are due to a fault in the test logic. A second set of test patterns are selected to induce errors to appear as the patterns are shifted, bit by bit, through the scan chain. The first patterns thereby determine that there are not errors in the fault monitoring logic itself, and the second patterns that the fault monitoring logic is detecting errors correctly.

Inventors

• 👤 David Cushing
• 👤 Edward Hutchings
• 👤 Elmer W. Carroll
• 👤 James Bertone

Bibliographic Details