US5043990A — Semiconductor integrated circuit device

Claim 1

Independent Claim 181 words

A semiconductor integrated circuit device comprising a first logic circuit which performs. in parallel with operations, generation of error detection codes and error detection of the operations, the first logic circuit comprising: a first circuit train including a plurality of operation circuits, connected in series with one another, for receiving input data, performing predetermined operations while said input data propagates through said series-connected operation circuits and providing output data; a second circuit train including a plurality of error detection code correction circuits, connected in series with one another, for receiving an error detection code input corresponding to said input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in said first circuit train, and outputting an error detection code corresponding to said output data; and at least one error detection circuit coupled to both the first and second circuit trains for performing comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train.

Claim 2

Dependent Claim 181 words

A semiconductor integrated circuit device comprising a first logic circuit which performs. in parallel with operations, generation of error detection codes and error detection of the operations, the first logic circuit comprising: a first circuit train including a plurality of operation circuits, connected in series with one another, for receiving input data, performing predetermined operations while said input data propagates through said series-connected operation circuits and providing output data; a second circuit train including a plurality of error detection code correction circuits, connected in series with one another, for receiving an error detection code input corresponding to said input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in said first circuit train, and outputting an error detection code corresponding to said output data; and at least one error detection circuit coupled to both the first and second circuit trains for performing comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train.

Claim 3

Dependent Claim 56 words

A semiconductor integrated circuit device according to claim 1, wherein said at least one error detection circuit includes one error detection circuit connected to the output of said first circuit train and another error detection circuit connected to the input of each operation circuit which does not propagate the parity error in said first circuit train.

Claim 4

Dependent Claim 55 words

A semiconductor integrated circuit device according to claim 1, further comprising a second logic circuit, the second logic circuit comprising: doubled operation circuits having the same function as one another and receiving the same input signal as one another; and a comparison circuit for comparing the outputs of said doubled operation circuits to each other.

Claim 5

Dependent Claim 100 words

A semiconductor integrated circuit device according to claim 3, wherein each of said doubled operation circuits comprises a logic circuit network for receiving input signal and performing logic operations thereon, a first switch circuit for pre-charging a parasitic capacitance at an interconnection in said logic circuit network, and a second switch circuit for deriving the output signal of said logic circuit network, the device further comprising a clock signal supply system divided into a supply sub-system for supplying the clock signal to said first switch circuit and another supply sub-system for supplying the clock signal to said second switch circuit.

Claim 6

Dependent Claim 40 words

A semiconductor integrated circuit device according to claim 4, comprising an ALU having an operation unit formed of said first logic circuit and a carry look-ahead generator unit formed of said second logic circuit and said clock signal supply system.

Claim 7

Dependent Claim 34 words

A semiconductor integrated circuit device according to claim 3, comprising an ALU having an operation unit formed of said first logic circuit and a carry look-ahead generator unit formed of said second logic circuit.

Claim 8

Dependent Claim 22 words

A semiconductor integrated circuit device according to claim 1, comprising an ALU having an operation unit formed of said first logic circuit.

Claim 9

Dependent Claim 128 words

A semiconductor integrated circuit device having a first logic circuit which comprises: doubled operation circuits having the same function as one another and receiving the same input signal as one another; a comparison circuit for comparing the outputs of the doubled operation circuits to each other; and a clock signal supply system including a first sub-system for supplying a clock signal to first switch circuits coupled to logic circuit networks of said doubled operation circuits for deriving respective output signals from said logic circuit networks of said doubled operation circuits, and a second sub-system for supplying a clock signal to second switch circuits formed in said doubled operation circuits for precharging said logic circuit networks, thereby performing diagnosis of said comparison circuit at a predetermined time of diagnosis.

Claim 10

Dependent Claim 128 words

A semiconductor integrated circuit device having a first logic circuit which comprises: doubled operation circuits having the same function as one another and receiving the same input signal as one another; a comparison circuit for comparing the outputs of the doubled operation circuits to each other; and a clock signal supply system including a first sub-system for supplying a clock signal to first switch circuits coupled to logic circuit networks of said doubled operation circuits for deriving respective output signals from said logic circuit networks of said doubled operation circuits, and a second sub-system for supplying a clock signal to second switch circuits formed in said doubled operation circuits for precharging said logic circuit networks, thereby performing diagnosis of said comparison circuit at a predetermined time of diagnosis.

Claim 11

Dependent Claim 171 words

A semiconductor integrated circuit device according to claim 8, further comprising a second logic circuit which performs in parallel with operations, generation of error detection codes and error detection of the operations, the second logic circuit comprising: a first circuit train including a series connection of plural stages of operation circuits for receiving input data, performing predetermined operations while said input data propagates through said operation circuits and providing output data; a second circuit train including a series connection of plural stages of error detection code correction circuits for receiving error detection code input corresponding to said input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in said first circuit train, and outputting an error detection code corresponding to said output data; and at least one error detection circuit for performing comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train.

Claim 12

Dependent Claim 34 words

A semiconductor integrated circuit device according to claim 9, comprising an ALU having a carry look-ahead generator unit formed of said first logic circuit and an operation unit formed of said second logic circuit.

Claim 13

Dependent Claim 189 words

A semiconductor integrated circuit device according to claim 8, wherein the supply of the clock signal to the respective operation circuits includes performing a logic operation upon reception of at least one input signal, connecting one end of the logic circuit network having a path between the two ends made conductive or non-conductive to a first power source, connecting one end of the first switch circuit to a second power source, connecting the other end of said logic circuit network and the other end of said first switch circuit to form a first node, connecting one end of a second switch circuit to said first node for deriving the signal at said first node, letting the other end of said second switch circuit be a second node, inserting a third switch circuit between said second node and said second power source, connecting a buffer circuit to said second node, supplying a first clock signal to a first and a third switch circuit in the operation circuit for outputting the signal at said second node through said buffer circuit, and supplying a second clock signal to the second switch circuit.

Claim 14

Dependent Claim 31 words

A semiconductor integrated circuit device according to claim 11, wherein said first, second, and third switch circuits, said logic circuit network and said buffer circuit are formed by using MOS FETs.

Claim 15

Dependent Claim 50 words

A semiconductor integrated circuit device according to claim 8, wherein the clock signals of said two sub-systems are formed from outputs of a clock generation circuit for generating clocks on the basis of an original clock signal inputted to the logic circuit and a control signal controlling the clock generation.

Claim 16

Dependent Claim 38 words

A semiconductor integrated circuit device according to claim 13, said clock generation circuit is formed on the same semiconductor chip on which is formed the logic circuit to which the output of said clock generation circuit is inputted.

Claim 17

Dependent Claim 150 words

A semiconductor integrated circuit device comprising a logic circuit which includes a plurality of operation circuits each including a first circuit for performing predetermined operation on input data and outputting output data, and a second circuit for performing predetermined operation on an error detection code input corresponding to said input data and outputting an error detection code corresponding to said output data, means for forming a data path by a first circuit train connecting said first circuits in the respective operation circuits, and means for forming an error detection code path by a second circuit train connecting said second circuits in the operation circuits which are connected mutually by said data path, wherein said logic circuit includes at least one error detection circuit for performing a check between the output data of said first circuit in the same operation circuit and the error detection code outputted from said second circuit.

Claim 18

Dependent Claim 150 words

A semiconductor integrated circuit device comprising a logic circuit which includes a plurality of operation circuits each including a first circuit for performing predetermined operation on input data and outputting output data, and a second circuit for performing predetermined operation on an error detection code input corresponding to said input data and outputting an error detection code corresponding to said output data, means for forming a data path by a first circuit train connecting said first circuits in the respective operation circuits, and means for forming an error detection code path by a second circuit train connecting said second circuits in the operation circuits which are connected mutually by said data path, wherein said logic circuit includes at least one error detection circuit for performing a check between the output data of said first circuit in the same operation circuit and the error detection code outputted from said second circuit.

Claim 19

Dependent Claim 17 words

A semiconductor integrated circuit device according to claim 15, comprising an ALU formed of said logic circuit.

Claim 20

Dependent Claim 28 words

A semiconductor integrated circuit device according to claim 16, wherein said operation circuit includes at least part of a latch circuit, a shift circuit and an adder/subtractor circuit.

Claim 21

Dependent Claim 177 words

A semiconductor integrated circuit device including an arithmetic logic unit, said arithmetic logic unit comprising: a data operation unit including a plurality of operation circuits, connected in series with one another, for receiving input data and for performing a predetermined arithmetic operation and/or a logic operation while said input data propagates sequentially through said plurality of operation circuits and providing for output data; and an error detection code generating unit including a plurality of error detection code correction circuits, connected in series with one another and respectively corresponding to said plurality of operation circuits, said error detection code generating unit applying a correction in correspondence to the operation of each of said operation circuits while an error detection code corresponding to said input data propagates sequentially through said plurality of error detection code correction circuits thereby to provide an error detection code corresponding to said output data, wherein the generation of the error detection code by said plurality of error detection code correction circuits is performed in parallel with the operations by said plurality of operation circuits.

Claim 22

Dependent Claim 177 words

A semiconductor integrated circuit device including an arithmetic logic unit, said arithmetic logic unit comprising: a data operation unit including a plurality of operation circuits, connected in series with one another, for receiving input data and for performing a predetermined arithmetic operation and/or a logic operation while said input data propagates sequentially through said plurality of operation circuits and providing for output data; and an error detection code generating unit including a plurality of error detection code correction circuits, connected in series with one another and respectively corresponding to said plurality of operation circuits, said error detection code generating unit applying a correction in correspondence to the operation of each of said operation circuits while an error detection code corresponding to said input data propagates sequentially through said plurality of error detection code correction circuits thereby to provide an error detection code corresponding to said output data, wherein the generation of the error detection code by said plurality of error detection code correction circuits is performed in parallel with the operations by said plurality of operation circuits.

Claim 23

Dependent Claim 60 words

A device according to claim 18, wherein an error detection unit including at least an error detection circuit, said error detection circuit performing a comparison and check operation of an output of the last stage of said plurality of operation circuits and an output of the error detection code correction circuit corresponding to the operation circuit of said last stage.

Claim 24

Dependent Claim 68 words

A device according to claim 19, wherein when said data operation unit includes an operation circuit to which no error is propagated, said error detection unit performs the comparison and check of an output of the operation circuit which is the preceding stage of the operation circuit to which no error is propagated and an output of the error detection code correction circuit corresponding to the operation circuit.

Claim 25

Dependent Claim 55 words

A device according to claim 18, 19 or 20, further comprising: a carry look-ahead generator unit including: doubled carry look-ahead generator circuits having the same function as one another and receiving the same input signal as one another; and a comparison circuit for comparing outputs of said doubled carry look-ahead generator circuits to each other.

Claim 26

Dependent Claim 101 words

A device according to claim 21, wherein each of said doubled carry look-ahead generator circuits comprises a first logic circuit network for receiving an input signal and performing logic operations thereon, a first switch circuit for precharging a parasitic capacitance at an interconnection in said logic circuit network, and a second switch circuit for deriving an output signal from said logic circuit network, the device further comprising a clock signal supply system divided into a supply sub-system for supplying a clock signal to said first switch circuit and another supply sub-system for supplying a clock signal to said second switch circuit.

Claim 27

Dependent Claim 117 words

A device according to claim 22, further comprising a second logic circuit which performs, in parallel with operations of said operation circuits, generation of error detection codes and error detection of the operations, the second logic circuit comprising: a first circuit train including plural stages of said operation circuits connected in series with one another; a second circuit train including plural stages of said error detection code correction circuits connected in series with one another; and at least one error detection circuit for performing a comparison and check operation on the output of the operation circuits in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train.

Claim 28

Dependent Claim 186 words

A device according to claim 22, wherein the supply of the clock signal to the respective operation circuits includes performing a logic operation upon reception of at least one input signal, connecting one end of the logic circuit network having a path between the two ends made conductive or non-conductive to a first power source, connecting one end of the first switch circuit to a second power source, connecting the other end of said logic circuit network and the other end of said first switch circuit to form a first node, connecting one end of a second switch circuit to said first node for deriving the signal at said first node, letting the other end of said second switch circuit be a second node, inserting a third switch circuit between said second node and said second power source, connecting a buffer circuit to said second node, supplying a first clock signal to a first and a third switch circuit in the operation circuit for outputting the signal at said second node through said buffer circuit, and supplying a second clock signal to the second switch circuit.

Claim 29

Dependent Claim 27 words

A device according to claim 24, wherein said first, second, and third switch circuits, said logic circuit network and said buffer circuit are formed by using MOSFETs.

Claim 30

Dependent Claim 47 words

A device according to claim 22, wherein the clock signals of said two sub-systems are formed from outputs of a clock generation circuit for generating clocks on the basis of an original clock signal inputted to the logic circuit and a control signal controlling the clock generation.

Claim 31

Dependent Claim 39 words

A semiconductor integrated circuit device according to claim 26, wherein said clock generation circuit is formed on the same semiconductor chip on which is formed the logic circuit to which the output of said clock generation circuit is inputted.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-08-26	1995-02-25	1995-08-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-08-26	1999-02-25	1999-08-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-08-26	2003-02-25	2003-08-27	$7700.00	Window Closed / Lapsed

Semiconductor integrated circuit device

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