ECC circuit failure detector/quick word verifier

Claim 2

A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failure in an error detection syndrome generation path in an error checking and correction (ECC) circuit, wherein said ECC circuit includes a check bit generator for generating check bits, G j , from the data bits in an ECC word, in accordance with an error correction code, wherein said ECC word includes a series of data bit fields and a set of memory check bits, C j , and wherein said error detection syndrome generation path generates syndrome bits, S j , from a comparison of said memory check bits, C j , to said generated check lists, G j , comprising: means for generating a bit, R k , for each of K data fields in the ECC word, by logically combining the data bits in said data field; means for comparing logical combinations of said R bits, to logical combinations of said memory check bits, C j , to generate H bits; and means for generating a logical combination of said H bits to quickly determine if all of the data bits in said ECC word are correct and/or for comparison to logical combinations of said syndrome bits to thereby independently determine whether there is a failure in said end detection syndrome generation path, but without cross-coupling with said check bit generator.

Claim 3

A circuit as defined in claim 1, wherein two and only two diagonal quadrants of said code matrix each are composed entirely of columns which have an even number of ones, and the other two diagonal quadrants are composed entirely of columns which have an odd number of ones.

Claim 4

A circuit as defined in claim 2, wherein said R bit generating means comprises means for generating a parity bit, P k , for each data field in said ECC word.

Claim 5

A circuit as defined in claim 3, wherein said H bit generating means comprises: means for combining said parity bits, P k , into logical combinations, to forms bits Q 1 and Q 2 ; and means for combining said memory check bits, C j , into two logical combination, to form bits M 1 and M 2 .

Claim 6

A circuit as defined in claim 4, wherein said memory check bit combining means includes means for forming bit M 1 from a logical combination of half of said check bits, C j , and for forming bit M 2 from a logical combination of the other half of said check bits, C j .

Claim 7

A circuit as defined in claim 5, wherein, for J check bits C 1 , C 2 , . . . C j , said memory check bit combining means include means for forming bit M 1 from a logical combination of C 1 . . . C J/2 , and means for forming bit M 2 from a logical combination of C J/2+1 . . . C J .

Claim 8

A circuit as defined in claim 6, wherein said memory check bit combining means includes means for forming bits M 1 , and M 2 in accordance with the following logical combinations: M.sub.1 =C.sub.1 ⊕C.sub.2 . . . ⊕C.sub.J/2, and M.sub.2 =C.sub.J/2+1 ⊕C.sub.J/2+2 . . . ⊕C.sub.J, where ⊕ is the exclusive OR function.

Claim 9

A circuit as defined in claim 7, wherein said parity bit combining means include means for forming bits Q 1 and Q 2 in accordance with the following logical combinations: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.K, where ⊕ is the exclusive OR function.

Claim 10

A circuit as defined in claim 8, wherein said H bit generating means includes means for generating bit H 1 from a logical combination of the bits Q 1 and M 2 , and for generating bit H 2 from a logical combination of the bits Q 2 and M 1 .

Claim 11

A circuit as defined in claim 12, wherein said H bit generating means includes means for generating the H 1 bit and the H 2 bit in accordance with the following functions: H.sub.1 =Q.sub.1 ⊕M.sub.2, and H.sub.2 =Q.sub.2 ⊕M.sub.1, where ⊕ is the exclusive OR functions.

Claim 12

A circuit as defined in claim 4, wherein said parity bit combining means includes means for forming bit Q 1 from a logical combination of half of said parity bits, P k , and means for forming bit Q 2 from a logical combination of the other half of said parity bits, P k .

Claim 13

A circuit as defined in claim 11, wherein, for K parity bits P 1 , P 2 , . . . P K , said parity bit combining means includes means for forming bit Q 1 from the logical combination of P 1 , . . . P K/2 , and means for forming bit Q 2 from the logical combination of P K/2+1 . . . P K .

Claim 14

A circuit as defined in claim 12, wherein said parity bit combining means include means for forming bits Q 1 and Q 2 in accordance with the following logical combinations: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.K, where ⊕ is the exclusive OR function.

Claim 15

A circuit as defined in claim 2, further comprising means for comparing said logical combination of said H bits to a logical combination of said syndrome bits, S j , to determine whether there is a failure in said error detection syndrome generator path.

Claim 16

A circuit as defined in claim 14, wherein said H and S bit comparing means includes means for logically combining said H bits to form a single bit D.

Claim 17

A circuit as defined in claim 15, wherein said H and S bit comparing means includes: means for logically combining said syndrome bits to form a single bit, E, and means for comparing bit D to bit E to generate an ECC check bit.

Claim 18

A circuit as defined in claim 16, wherein said D and E bit comparing means compares said bits in accordance with the function ECC CHECK BIT=D⊕E, where ⊕ is the exclusive OR function.

Claim 19

A circuit as defined in claim 14, wherein said parity bit generating means includes means for generating a parity bit in accordance with the function P.sub.k =D.sub.1 ⊕D.sub.2 . . . ⊕D.sub.N for each data field, wherein there are N data bits in each data field and wherein ⊕ is the exclusive OR function.

Claim 20

A circuit as defined in claim 14, wherein said R bit generating means comprises means for generating a parity bit, P k , for each data field in said ECC word.

Claim 21

A circuit as defined in claim 19, wherein said H bit generating means comprises: means for combining said parity bits, P k , into two logical combinations, to form bits Q 1 and Q 2 ; and means for combining said memory check bits, C j , into two logical combinations to form bits M 1 and M 2 .

Claim 22

A circuit as defined in claim 20, wherein said memory check bit combining means includes means for forming bit M 1 from a logical combination of half of said check bits, C j , and for forming bit M 2 from a logical combination of the other half of said check bits, C j .

Claim 23

A circuit as defined in claim 21, wherein said parity bit combining means includes means for forming bit Q 1 from a logical combination of half of said parity bits, P k , and means for forming bit Q 2 from a logical combination of the other half of said parity bits.

Claim 24

A circuit as defined in claim 21, wherein, for J check bits C 1 , C 2 , . . . C J , said memory check bit combining means includes means for forming bits M 1 and M 2 in accordance with the following logical combinations: M.sub.1 =C.sub.1 ⊕C.sub.2 . . . ⊕C.sub.J/2, and M.sub.2 =C.sub.J/2+1 ⊕C.sub.J/2+2 . . . ⊕C.sub.J, where ⊕ is the exclusive OR function.

Claim 25

A circuit as defined in claim 23, wherein, for K parity bits P 1 , P 2 , . . . P K , said parity bit combining means includes means for forming bit Q 1 from the logical combination of P 1 , . . . P K/2 , and means for forming bit Q 2 from the logical combination of P K/2+1 . . . P K .

Claim 26

A circuit as defined in claim 23, wherein said parity bit combining means includes means for forming bits Q 1 and Q 2 in accordance with the following logical combinations: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.K, where ⊕ is the exclusive OR function.

Claim 27

A circuit as defined in claim 25, wherein said H bit generating means includes means for generating bit H 1 from a logical combination of Q 1 and M 2 , and for generating H 2 from a logical combination of Q 2 and M 1 .

Claim 28

A circuit as defined in claim 26, wherein said H bit generating means includes means for generating the H 1 bit and the H 2 bit in accordance with the following functions: H.sub.1 =Q.sub.1 ⊕M.sub.2, and H.sub.2 =Q.sub.2 ⊕M.sub.1, where ⊕ is the exclusive OR function.

Claim 29

A circuit as defined in claim 27, wherein said H and S bit comparing means includes means for logically combining said H bits to form a single bit D.

Claim 30

A circuit as defined in claim 28 wherein said H and S bit comparing means includes: means for logically combining said syndrome bits to form a single bit E, and means for comparing bit D to bit E to generate an ECC check bit.

Claim 31

A circuit as defined in claim 29, wherein said D and E comparing means compares said bits in accordance with the function ECC CHECK=D⊕E, where ⊕ is the exclusive OR function.

Claim 34

A method as defined in claim 31, wherein said parity bit combining step includes the step of forming said bits Q 1 and Q 2 in accordance with the following logical conditions: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.K, where ⊕ is the exclusive OR function.

Claim 35

A method as defined in claim 31, wherein two and only two diagonal quadrants of said code matrix are each composed entirely of columns which have an even number of ones, and the other two diagonal quadrants are composed entirely of columns having an odd number of ones.

Claim 36

A method as defined in claim 33, wherein said R k bit generating step comprises the step of generating a parity bit, P k , for each of said K data fields in said ECC word.

Claim 37

A method as defined in claim 34, wherein said H bit generating step comprises the steps of combining said parity bits, P k , into two separate logical combinations to form bits Q 1 and Q 2 , and combining said memory check bits, C j , into two separate logical combinations to form the bits M 1 and M 2 .

Claim 38

A method as defined in claim 35, wherein said parity bit generating step includes the step of generating a parity bit in accordance with the function P.sub.k =D.sub.1 ⊕D.sub.2 . . . ⊕D.sub.N, for each bit data field, where there are N data bits in each data field and wherein ⊕ is the exclusive OR function.

Claim 39

A method as defined in claim 35, wherein said H bit generating step includes the step of generating the H 1 bit and the H 2 bit in accordance with the following functions: H.sub.1 =Q.sub.1 ⊕M.sub.2, and H.sub.2 =Q.sub.2 ⊕M.sub.1, where ⊕ is the exclusive OR function.

Claim 40

A method as defined in claim 37, further comprising the step of comparing said logical combination of said H bits to a logical combination of said syndrome bits, S j , to determine whether there is a failure in said error detection syndrome generation path.

Claim 41

A method as defined in claim 38, wherein said H and S bit comparing step includes the step of logically combining said H bits to form a single bit D, and logically combining said syndrome bits, S j , to form a single bit E; and comparing bit D to bit E to generate an ECC check bit.

Claim 42

A method as defined in claim 39, wherein said D and E bit comparing means compares said bits in accordance with the function: ECC CHECK BIT=D⊕E, where ⊕ is the exclusive OR function.

Claim 43

A method as defined in claim 35, wherein for J check bits C 1 , C 2 , . . . C J , said check bit combining step comprises the step of forming bit M 1 from a logical combination of C 1 . . . C J/2 , and forming bit M 2 from a logical combination of C J/2+1 . . . C J .

Claim 44

A method as defined in claim 41, wherein said check bit combining step comprises the step of forming bits M 1 and M 2 in accordance with the following logical combinations: M.sub.1 =C.sub.1 ⊕C.sub.2 . . . ⊕C.sub.J/2, and M.sub.2 =C.sub.J/2+1 ⊕C.sub.J/2+2 . . . ⊕C.sub.J, where + is the exclusive OR function.

Claim 45

A method as defined in claim 41, wherein for K parity bits P 1 , P 2 , . . . P K , said parity bit combining step comprises the step of forming bit Q 1 , from the logical combination of P 1 , . . . P K/2 , and forming bit Q 2 from the logical combination of P K/2+1 . . . P K .

Claim 46

A method as defined in claim 43, wherein said parity bit combining step includes the step of forming said bits Q 1 and Q 2 in accordance with the following logical combinations: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.K, where ⊕ is the exclusive OR function.

Claim 47

A method as defined in claim 43, wherein said H bit generating step includes the step of generating a bit H 1 from a logical combination of bits Q 1 and M 2 , and generating a bit H 2 from a logical combination of bits Q 2 and M 1 .

Claim 48

A method as defined in claim 45, wherein said H bit generating step includes the step of generating the H 1 bit and the H 2 bit in accordance with the following functions: H.sub.1 =Q.sub.1 ⊕M.sub.2, and H.sub.2 =Q.sub.2 ⊕M.sub.1, where ⊕ is the exclusive OR function.

Claim 49

A circuit for detecting failures in an error detection syndrome generation path of an error checking and correcting (ECC) circuit which ECC circuit uses an error correcting code having two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones, wherein said ECC circuit includes a check bit generator for generating check bits, G j , from the data bits in an ECC word in accordance with said error correcting code, wherein said ECC word includes a series of data bit fields and a set of memory check bits, C j , and wherein said error detection syndrome generation path generates syndrome bits, S j , from a comparison of said memory check bits, C j , to said generated check bits, G j , comprising: means for generating parity bits P 1 , P 2 , . . . P K , one for each of K data fields in said ECC word; means for logically combining said parity bits, P k , to form bits Q 1 and Q 2 , in accordance with the logical combinations: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.k, where ⊕ is the exclusive OR function; means for logically combining said check bits, C j , to form bits M 1 and M 2 , in accordance with the logical combinations: M.sub.1 =C.sub.1 ⊕C.sub.2 . . . ⊕C.sub.J/2, and M.sub.2 =C.sub.J/2+1 ⊕C.sub.J/2+2 . . . ⊕C.sub.J, where there are J check bits; means for logically combining said Q and M bits to form the bits H 1 and H 2 in accordance with the following logical combinations: H.sub.1 =Q.sub.1 ⊕M.sub.2, and H.sub.2 =Q.sub.2 ⊕M.sub.1 ; means for generating the function D=H 1 ⊕H 2 ; means for adding said syndrome bits, S j , to form a single bit E; and means for generating an ECC CHECK BIT with the function ECC CHECK BIT=D⊕E, wherein said ECC CHECK BIT independently indicates whether there is a failure in said error detection syndrome generation path without cross-coupling with said check bit generator.

Claim 50

A circuit for detecting failures in an error detection syndrome generation path of an error checking and correcting (ECC) circuit which ECC circuit uses an error correcting code having two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones, wherein said ECC circuit includes a check bit generator for generating check bits, G j , from the data bits in an ECC word in accordance with said error correcting code, wherein said ECC word includes a series of data bit fields and a set of memory check bits, C j , and wherein said error detection syndrome generation path generates syndrome bits, S j , from a comparison of said memory check bits, C j , to said generated check bits, G j , comprising: means for generating parity bits P 1 , P 2 , . . . P K , one for each of K data fields in said ECC word; means for logically combining said parity bits, P k , to form bits Q 1 and Q 2 , in accordance with the logical combinations: Q.sub.1 =P.sub.1 ⊕P.sub.2 . . . ⊕P.sub.K/2, and Q.sub.2 =P.sub.K/2+1 ⊕P.sub.K/2+2 . . . ⊕P.sub.k, where ⊕ is the exclusive OR function; means for logically combining said check bits, C j , to form bits M 1 and M 2 , in accordance with the logical combinations: M.sub.1 =C.sub.1 ⊕C.sub.2 . . . ⊕C.sub.J/2, and M.sub.2 =C.sub.J/2+1 ⊕C.sub.J/2+2 . . . ⊕C.sub.J, where there are J check bits; means for logically combining said Q and M bits to form the bits H 1 and H 2 in accordance with the following logical combinations: H.sub.1 =Q.sub.1 ⊕M.sub.2, and H.sub.2 =Q.sub.2 ⊕M.sub.1 ; means for generating the function D=H 1 ⊕H 2 ; means for adding said syndrome bits, S j , to form a single bit E; and means for generating an ECC CHECK BIT with the function ECC CHECK BIT=D⊕E, wherein said ECC CHECK BIT independently indicates whether there is a failure in said error detection syndrome generation path without cross-coupling with said check bit generator.