US4669081A
Expired / Lapsed
US
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LSI fault insertion
Assignee: M&T HARSHAW
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Filing: 1986-02-04
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Granted: 1987-05-26
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Expires: 2006-02-04
Abstract
Abstract Apparatus and method for providing programmable fault insertion circuitry in a large scale integrated (LSI) circuit device thereby eliminating the need for external switches or relays to create faults. A fault parameter word is stored in a register and the outputs of the register are decoded to select the fault condition to be inserted by an interfacing circuit to the logic being tested. Test vectors and the fault parameter word are generated by a controller coupled to the integrated circuit and a test response from the integrated circuit is examined by the controller.
Inventors
- 👤 James K. Mathewes, Jr.
- 👤 C. W. Gustav Eifrig
- 👤 Jan S. Herman
- 👤 H. Frank Howes
- 👤 Charles O. Schulz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2215; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318547
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
100 words
In a large scale integrated circuit including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, fault insertion circuitry resident in said integrated circuit comprising: register means having a serial input, a serial output and a parallel output for storing a fault parameter word, said register means being serially coupled into an input line to said serially accessed registers; and fault generation means coupled between said parallel output of said register means and said plurality of logic for generating a fault condition specified by said fault parameter word.
Claim 2
Dependent Claim
100 words
In a large scale integrated circuit including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, fault insertion circuitry resident in said integrated circuit comprising: register means having a serial input, a serial output and a parallel output for storing a fault parameter word, said register means being serially coupled into an input line to said serially accessed registers; and fault generation means coupled between said parallel output of said register means and said plurality of logic for generating a fault condition specified by said fault parameter word.
Claim 3
Dependent Claim
24 words
The fault insertion circuitry as recited in claim 1 wherein: said register means provides for fault programmability in response to said fault parameter word.
Claim 4
Dependent Claim
22 words
The fault insertion circuitry as recited in claim 1 wherein: said fault generation means comprises decoding means for selecting said fault condition.
Claim 5
Dependent Claim
26 words
The fault insertion circuitry as recited in claim 1 wherein: said fault generation means comprises means for interfacing said fault condition to said plurality of logic.
Claim 6
Dependent Claim
22 words
The fault insertion circuitry as recited in claim 1 wherein: said fault condition comprises a signal stuck at a logic one level.
Claim 7
Dependent Claim
22 words
The fault insertion circuitry as recited in claim 1 wherein: said fault condition comprises a signal stuck at a logic zero level.
Claim 8
Dependent Claim
19 words
The fault insertion circuitry as recited in claim 1 wherein: said fault condition comprises disabling a tri-state driver means.
Claim 9
Dependent Claim
127 words
In a large scale integrated circuit including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, fault insertion circuitry resident in said integrated circuit comprising: register means having a serial input, a serial output and a parallel output for storing a fault parameter word, said register means being serially coupled into an input line of said serially accessed registers; means coupled to said parallel output of said register means for decoding said fault parameter word thereby asserting one of a plurality of fault conditions specified by said fault parameter word; and means coupled to said decoding means and said plurality of logic for interfacing each fault condition to a portion of said logic being tested.
Claim 10
Dependent Claim
127 words
In a large scale integrated circuit including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, fault insertion circuitry resident in said integrated circuit comprising: register means having a serial input, a serial output and a parallel output for storing a fault parameter word, said register means being serially coupled into an input line of said serially accessed registers; means coupled to said parallel output of said register means for decoding said fault parameter word thereby asserting one of a plurality of fault conditions specified by said fault parameter word; and means coupled to said decoding means and said plurality of logic for interfacing each fault condition to a portion of said logic being tested.
Claim 11
Dependent Claim
23 words
The fault insertion circuitry as recited in claim 8 wherein: said register means provides fault programmability in response to said fault parameter word.
Claim 12
Dependent Claim
77 words
The fault insertion circuitry as recited in claim 8 wherein: a first one of said interfacing means provides a stuck at one logic level to a first portion of said logic being tested in response to a first one of said fault conditions; and a second one of said interfacing means provides a stuck at zero logic level to a second portion of said logic being tested in response to a second one of said fault conditions.
Claim 13
Dependent Claim
44 words
The fault insertion circuitry as recited in claim 8 wherein: a third one of said interfacing means provides a disable signal for testing tri-state driver means coupled together at a common output, said disable signal disabling at least one of said tri-state driver means.
Claim 14
Dependent Claim
169 words
A fault insertion test system for verifying fault detection in an integrated circuit having a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable comprising: fault insertion circuit means resident in said integrated circuit comprising (a) register means having a serial input, a serial output and a parallel output for storing a fault parameter word, said register means being serially coupled into an input line to said serially accessed registers and (b) fault generation means coupled between said parallel output of said register means and said plurality of logic for generating a fault condition specified by said fault parameter word; and controlling means coupled to said integrated circuit for providing a first test vector word and said fault parameter word to said input line, a second test vector word to data inputs of said integrated circuit, and testing a response from a serial output line and data outputs of said integrated circuit resulting from said fault insertion condition.
Claim 15
Dependent Claim
169 words
A fault insertion test system for verifying fault detection in an integrated circuit having a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable comprising: fault insertion circuit means resident in said integrated circuit comprising (a) register means having a serial input, a serial output and a parallel output for storing a fault parameter word, said register means being serially coupled into an input line to said serially accessed registers and (b) fault generation means coupled between said parallel output of said register means and said plurality of logic for generating a fault condition specified by said fault parameter word; and controlling means coupled to said integrated circuit for providing a first test vector word and said fault parameter word to said input line, a second test vector word to data inputs of said integrated circuit, and testing a response from a serial output line and data outputs of said integrated circuit resulting from said fault insertion condition.
Claim 16
Dependent Claim
24 words
The fault insertion test system as recited in claim 12 wherein: said register means provides fault programmability in response to said fault parameter word.
Claim 17
Dependent Claim
29 words
The fault insertion test system as recited in claim 12 wherein: said fault generation means provides a stuck at one logic level fault condition to said logic being tested.
Claim 18
Dependent Claim
29 words
The fault insertion test system as recited in claim 12 wherein: said fault generation means provides a stuck at zero logic level fault condition to said logic being tested.
Claim 19
Dependent Claim
41 words
The fault insertion test system as recited in claim 12 wherein: said fault generation means provides a disable signal for testing tri-state driver means coupled together at a common output, said disable signal disabling at least one of said driver means.
Claim 20
Independent Claim
101 words
The method of fault insertion in a large scale integrated circuit, including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, by fault insertion circuitry resident in said integrated circuit comprising the steps of: storing a fault parameter word in a register means having a serial input, a serial output and a parallel output, said register means being serially coupled into an input line to said serially accessed registers; generating a fault condition specified by said fault parameter word; and coupling said fault condition to said plurality of logic.
Claim 21
Independent Claim
101 words
The method of fault insertion in a large scale integrated circuit, including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, by fault insertion circuitry resident in said integrated circuit comprising the steps of: storing a fault parameter word in a register means having a serial input, a serial output and a parallel output, said register means being serially coupled into an input line to said serially accessed registers; generating a fault condition specified by said fault parameter word; and coupling said fault condition to said plurality of logic.
Claim 22
Dependent Claim
28 words
The method as recited in claim 17 wherein: said step of generating a fault condition comprises the step of generating a stuck at a logic one level signal.
Claim 23
Dependent Claim
27 words
The method as recited in claim 17 wherein: said step of generating a fault condition comprises the step of generating a stuck at a zero level signal.
Claim 24
Dependent Claim
28 words
The method as recited in claim 17 wherein: said step of generating a fault condition comprises the step of generating a disabling signal for a tri-state driver means.
Claim 25
Independent Claim
119 words
The method of fault insertion in a large scale integrated circuit, including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, by fault insertion circuitry resident in said integrated circuit comprising the steps of: providing a fault parameter word to a register means having a serial input, a serial output and a parallel output, said register means being serially coupled into an input line to said serially accessed registers; decoding said fault parameter word available at said parallel output of said register means for asserting one of a plurality of fault conditions; and interfacing each of said fault conditions to a portion of said logic being tested.
Claim 26
Independent Claim
119 words
The method of fault insertion in a large scale integrated circuit, including a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, by fault insertion circuitry resident in said integrated circuit comprising the steps of: providing a fault parameter word to a register means having a serial input, a serial output and a parallel output, said register means being serially coupled into an input line to said serially accessed registers; decoding said fault parameter word available at said parallel output of said register means for asserting one of a plurality of fault conditions; and interfacing each of said fault conditions to a portion of said logic being tested.
Claim 27
Dependent Claim
32 words
The method as recited in claim 21 wherein: said step of interfacing said fault conditions to said logic being tested comprises the step of providing a stuck at one logic level signal.
Claim 28
Dependent Claim
33 words
The method as recited in claim 21 wherein: said step of interfacing said fault conditions to said logic being tested comprises the step of providing a stuck at a zero logic level signal.
Claim 29
Dependent Claim
50 words
The method as recited in claim 21 wherein: said step of interfacing said fault conditions to said logic being tested comprises the step of providing a disable signal to tri-state driver means having common outputs coupled together, whereby said disable signal disables at least one of said tri-state driver means.
Claim 30
Independent Claim
174 words
The method of fault insertion for verifying fault detection in a large scale integrated circuit having a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, by fault insertion circuitry resident in said integrated circuit comprising: loading a first test vector word into said serially accessed registers; providing a second test vector word to data inputs of said integrated circuit; storing a fault parameter word in a register means having a serial input, a serial output and a parallel output, said register means being serially coupled into an input line to said serially accessed registers; decoding said fault parameter word for asserting one of a plurality of fault conditions; interfacing each of said fault conditions to a portion of said logic being tested; and testing a response from a serial output line and data outputs of said integrated circuit resulting from said first and second test vectors and said fault insertion conditions provided by said fault parameter word to said serial input line.
Claim 31
Independent Claim
174 words
The method of fault insertion for verifying fault detection in a large scale integrated circuit having a plurality of logic arranged for internal logic states to be held in serially accessed registers which are observable and controllable, by fault insertion circuitry resident in said integrated circuit comprising: loading a first test vector word into said serially accessed registers; providing a second test vector word to data inputs of said integrated circuit; storing a fault parameter word in a register means having a serial input, a serial output and a parallel output, said register means being serially coupled into an input line to said serially accessed registers; decoding said fault parameter word for asserting one of a plurality of fault conditions; interfacing each of said fault conditions to a portion of said logic being tested; and testing a response from a serial output line and data outputs of said integrated circuit resulting from said first and second test vectors and said fault insertion conditions provided by said fault parameter word to said serial input line.
Claim 32
Dependent Claim
48 words
The method as recited in claim 25 wherein: said step of testing a response to said first and second test vectors and said fault insertion conditions includes using a controlling means coupled to said integrated circuit for providing said test vectors and fault conditions and examining said response.
Claim 33
Dependent Claim
33 words
The method as recited in claim 25 wherein: said step of interfacing said fault conditions to said logic being tested comprises the step of providing a stuck at a one logic level signal.
Claim 34
Dependent Claim
33 words
The method as recited in claim 25 wherein: said step of interfacing said fault conditions to said logic being tested comprises the step of providing a stuck at a zero logic level signal.
Claim 35
Dependent Claim
50 words
The method as recited in claim 25 wherein: said step of interfacing said fault conditions to said logic being tested comprises the step of providing a disable signal to tri-state driver means having common outputs coupled together whereby said disable signal disables at least one of said tri-state driver means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-25 | 1990-11-24 | 1991-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-25 | 1994-11-24 | 1995-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-25 | 1998-11-24 | 1999-05-26 | $7700.00 | Window Closed / Lapsed |