Micro-coded built-in self-test apparatus for a memory array

Claim 1

A micro-coded built-in self-test apparatus for a memory array comprising in combination: a memory cell array having a predetermined number of cells, said memory cell array receiving input data which includes test data and control signals and providing an output data signal, said memory cell array including a row decoder and a column decoder, a read only memory storing a plurality of micro-instructions therein, and a sequencer and control means operatively connected to said read only memory to receive said micro-instructions therefrom and to generate a micro-code memory address signal, said sequencer and control means including: a micro-code instruction register to receive said micro-instructions from said read only memory, means for decoding, said decoding means decoding the instruction bit of said micro-instructions and providing a first control signal and a second control signal, a control signal/compaction and detection logic unit receiving said first control signal and said micro-instructions from said decoding means, said control signal/compaction and detection logic unit providing said control signals and said test data to said memory cell array, said control signal/compaction and detection logic unit receiving said output data signal from said memory cell array and providing a go/nogo signal in response thereto, an address generation logic unit receiving said micro-instructions from said micro-coder instruction register, said address generation logic unit receiving said second control signal from said decoding means and receiving said go/nogo signal from said control signal/compaction and detection logic unit, said address generation logic unit generating the next micro-code address, and a micro-code memory address register to receive said next micro-code address from said address generation logic unit, said micro-code memory address register providing said micro-code memory address signal to said read only memory, wherein said go/nogo signal reflects the status of said memory cell array.