US5073891A
Expired / Lapsed
US
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Method and apparatus for testing memory
Assignee: Intel Corp
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Filing: 1990-02-14
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Granted: 1991-12-17
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Expires: 2010-02-14
Abstract
Abstract A method and apparatus for testing the integrity of a memory storing controlled information. The data array semiconductor memory that stores controlled information such as instructions or microcodes, is partitioned into two halves. One half stores the test pattern information, the other half stores the test program. An instruction test (I-TEST) instruction is provided for testing the instruction cache data array. The test program comprises a pair of I-TEST instruction and checkerboard pattern forming an instruction equivalent to the width of the data array. The I-TEST instruction runs in dual instruction mode with a floating point instruction replaced by the test pattern. The I-TEST program is executed by transferring its test pattern data from the instruction cache data array to a register R1 in the register file, and then comparing that data with the expected value located in a register other than R1 in the register file. If any comparison fails, then a defect in the data array will have been detected. To fully cover the data array, the I-TEST program must be repeated with test patterns located in the other half of the data array and swapped by a swapper which is coupled to the data array. The swapping action is accomplished by simply aligning the I-TEST instruction on the odd eight-byte boundaries rather than the even byte boundary.
Inventors
- 👤 Piyush G. Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G11C29/04; G11C29/08; G11C29/12; G11C29/14
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
275 words
A method of testing the integrity of an instruction cache of a microprocessor, comprising: (a) dividing a data array of the instruction cache into a first partition and a second partition, wherein the first partition includes a first memory location and the second partition includes a second memory location; (b) loading an instruction-test instruction into the first memory location of the first partition and a test pattern into the second memory location of the second partition; (c) applying the instruction-test instruction to an execution unit of the microprocessor and the test pattern to a control unit of the microprocessor; (d) comparing the test pattern with a predetermined value; (e) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure and stopping the testing, wherein the steps (c)-(e) are controlled by the instruction-test instruction; and (f) if the test pattern matches the predetermined value, then performing a swap operation by loading the instruction-test instruction into the second memory location of second partition and the test pattern into the first memory location of the first partition and performing the following steps; (i) applying the instruction-test instruction from the second memory location of second partition to the execution unit of the microprocessor and the test pattern from the first memory location of the first partition to the control unit of the microprocessor; (ii) comparing the test pattern read from the first memory location of the first partition with the predetermined value; (iii) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure, wherein the steps (i)-(iii) are controlled by the instruction-test instruction.
Claim 2
Independent Claim
275 words
A method of testing the integrity of an instruction cache of a microprocessor, comprising: (a) dividing a data array of the instruction cache into a first partition and a second partition, wherein the first partition includes a first memory location and the second partition includes a second memory location; (b) loading an instruction-test instruction into the first memory location of the first partition and a test pattern into the second memory location of the second partition; (c) applying the instruction-test instruction to an execution unit of the microprocessor and the test pattern to a control unit of the microprocessor; (d) comparing the test pattern with a predetermined value; (e) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure and stopping the testing, wherein the steps (c)-(e) are controlled by the instruction-test instruction; and (f) if the test pattern matches the predetermined value, then performing a swap operation by loading the instruction-test instruction into the second memory location of second partition and the test pattern into the first memory location of the first partition and performing the following steps; (i) applying the instruction-test instruction from the second memory location of second partition to the execution unit of the microprocessor and the test pattern from the first memory location of the first partition to the control unit of the microprocessor; (ii) comparing the test pattern read from the first memory location of the first partition with the predetermined value; (iii) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure, wherein the steps (i)-(iii) are controlled by the instruction-test instruction.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein the steps (c)-(e) are executed in a dual instruction mode of the microprocessor.
Claim 4
Dependent Claim
24 words
The method of claim 1, wherein the execution unit is an integer execution unit and the control unit is a floating point control unit.
Claim 5
Dependent Claim
211 words
An instruction cache of a microprocessor, comprising: (A) a data array having a first partition and a second partition; (B) instruction-test instruction means stored in the data array for testing integrity of the data array, wherein the instruction-test instruction means includes (1) an instruction-test instruction stored at the first partition and (2) a test pattern stored at the second partition, wherein the instruction-test instruction means is operated in a dual instruction mode; and (C) output swapper means coupled to (1) the data array for receiving the instruction-test instruction and the test pattern from the data array, and to (2) an integer execution unit of the microprocessor and a floating point control unit of the microprocessor for selectively coupling the instruction-test instruction to the integer execution unit and the test pattern to the floating point control unit, wherein the instruction-test instruction controls the output swapper means to selectively couple the instruction-test instruction to the integer execution unit and the test pattern to the floating point control unit, wherein the instruction-test instruction causes the integer execution unit to compare the test pattern in the floating control unit with a predetermined value, wherein the integer execution unit issues a signal indicative of a failure if the test pattern does not match the predetermined value.
Claim 6
Dependent Claim
211 words
An instruction cache of a microprocessor, comprising: (A) a data array having a first partition and a second partition; (B) instruction-test instruction means stored in the data array for testing integrity of the data array, wherein the instruction-test instruction means includes (1) an instruction-test instruction stored at the first partition and (2) a test pattern stored at the second partition, wherein the instruction-test instruction means is operated in a dual instruction mode; and (C) output swapper means coupled to (1) the data array for receiving the instruction-test instruction and the test pattern from the data array, and to (2) an integer execution unit of the microprocessor and a floating point control unit of the microprocessor for selectively coupling the instruction-test instruction to the integer execution unit and the test pattern to the floating point control unit, wherein the instruction-test instruction controls the output swapper means to selectively couple the instruction-test instruction to the integer execution unit and the test pattern to the floating point control unit, wherein the instruction-test instruction causes the integer execution unit to compare the test pattern in the floating control unit with a predetermined value, wherein the integer execution unit issues a signal indicative of a failure if the test pattern does not match the predetermined value.
Claim 7
Dependent Claim
50 words
The instruction cache of claims 4, further comprising a fail register having a first state which indicates that a defect in the data array is tested, wherein the fail register is in the first state when the comparison of the test pattern and the predetermined value results in a mismatch.
Claim 8
Dependent Claim
36 words
The instruction cache of claim 4, wherein the output swapper means simultaneously couples the instruction-test instruction to the integer execution unit and the test pattern to the floating point control unit in the dual instruction mode.
Claim 9
Independent Claim
456 words
A method of testing the integrity of an instruction cache of a microprocessor, comprising: (a) dividing a data array of the instruction cache into a first partition and a second partition, wherein the first partition includes a first plurality of memory locations, including a first memory location, wherein the second partition includes a second plurality of memory locations, including a second memory location; (b) loading an instruction-test instruction into each of the first plurality of memory locations in the first partition, and loading a test pattern into each of the second plurality of memory locations in the second partition; (c) applying the instruction-test instruction from the first memory location in the first partition to an execution unit of the microprocessor and the test pattern from second memory location in the second partition to a control unit of the microprocessor; (d) comparing the test pattern with a predetermined value; (e) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure and stopping the testing, wherein steps (c)-(e) are controlled by the instruction-test instruction; (f) if the test pattern matches the predetermined value, then repeating steps (c)-(e) until the second partition has been tested entirely, wherein upon each repetition, a next one of the first plurality of memory locations in the first partition becomes the first memory location, and a next one of the second plurality of memory locations in the second partition becomes the second memory location; and (g) if the second partition has been tested entirely, then performing a swap operation by loading the instruction-test instruction into the second plurality of memory locations of the second partition and loading the test pattern into the first plurality of memory locations of the first partition and performing the following steps: (i) applying the instruction-test instruction from the second memory location of the second partition to the execution unit of the microprocessor and the test pattern from the first memory location of the first partition to the control unit of the microprocessor; (ii) comparing the test pattern read from the the first memory location of the first partition with the predetermined value; (iii) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure and stopping the testing, wherein the steps (i)-(iii) are controlled by the instruction-test instruction; and (iv) if the test pattern matches the predetermined value, then repeating the steps (i)-(iii) until the first partition has been tested entirely, wherein upon each repetition, a next one of the first plurality of memory locations in the first partition becomes the first memory location, and a next one of the second plurality of memory locations in the second partition becomes the second memory location.
Claim 10
Independent Claim
456 words
A method of testing the integrity of an instruction cache of a microprocessor, comprising: (a) dividing a data array of the instruction cache into a first partition and a second partition, wherein the first partition includes a first plurality of memory locations, including a first memory location, wherein the second partition includes a second plurality of memory locations, including a second memory location; (b) loading an instruction-test instruction into each of the first plurality of memory locations in the first partition, and loading a test pattern into each of the second plurality of memory locations in the second partition; (c) applying the instruction-test instruction from the first memory location in the first partition to an execution unit of the microprocessor and the test pattern from second memory location in the second partition to a control unit of the microprocessor; (d) comparing the test pattern with a predetermined value; (e) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure and stopping the testing, wherein steps (c)-(e) are controlled by the instruction-test instruction; (f) if the test pattern matches the predetermined value, then repeating steps (c)-(e) until the second partition has been tested entirely, wherein upon each repetition, a next one of the first plurality of memory locations in the first partition becomes the first memory location, and a next one of the second plurality of memory locations in the second partition becomes the second memory location; and (g) if the second partition has been tested entirely, then performing a swap operation by loading the instruction-test instruction into the second plurality of memory locations of the second partition and loading the test pattern into the first plurality of memory locations of the first partition and performing the following steps: (i) applying the instruction-test instruction from the second memory location of the second partition to the execution unit of the microprocessor and the test pattern from the first memory location of the first partition to the control unit of the microprocessor; (ii) comparing the test pattern read from the the first memory location of the first partition with the predetermined value; (iii) if the test pattern does not match the predetermined value, then issuing a signal indicative of a failure and stopping the testing, wherein the steps (i)-(iii) are controlled by the instruction-test instruction; and (iv) if the test pattern matches the predetermined value, then repeating the steps (i)-(iii) until the first partition has been tested entirely, wherein upon each repetition, a next one of the first plurality of memory locations in the first partition becomes the first memory location, and a next one of the second plurality of memory locations in the second partition becomes the second memory location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |