Semiconductor device incorporating memory test pattern generating circuit

Claim 2

A semiconductor device comprising: a memory cell array accessed by address signals; a test pattern generating circuit means for generating test pattern data in response to receiving and logically processing a part of said address signals and a control signal, wherein the pattern of said data is changed in accordance with change of said part of said address signals; and a selector operatively connecting said memory cell array and said test pattern generating circuit means, wherein said test pattern data is transmitted through said selector to said memory cell array in a test mode.

Claim 3

A semiconductor device according to claim 1, wherein the part of said said address signals logically processed by said test pattern generating circuit means is a least significant bit signal.

Claim 4

A semiconductor device according to claim 2, wherein said test pattern is generated in said test pattern generating circuit means by logically processing said least significant bit signal, the inverted signal of said least significant bit signal, said control signal, and the inverted signal of said control signal.

Claim 5

A semiconductor device according to claim 2, wherein said test pattern is generated in said test pattern generating circuit means by logically processing said least significant bit signal of row address signals, said least significant bit signal of column address signals, said control signal, and the inverted signal of said control signal.

Claim 6

The semiconductor device of claim 1, wherein said test pattern generating circuit means comprises: at least a first and a second part of AND gates, wherein a first AND gate of said first pair receives one input from said control signal, and a second input from an inverted signal of at least significant bit signal of said part of said address signals, and wherein a second AND gate of said first pair receives one input from an inverted signal of said control signal, and a second input from said least significant bit signal of said part of said address signals, and wherein a first AND gate of said second pair receives one input from said inverted control signal and a second input from said inverted least significant bit signal of said part of the address signals, and wherein a second AND gate of said second pair receive one input from said control signal and a second input from said least significant bit signal of said part of the address signals, and wherein the outputs of said first pair of AND gates are input to a first OR gate, and the outputs of said second pair of AND gates are input to a second OR gate, the outputs of said first and second OR gates being connected to said selector, such that upon the providing of said control signal, the outputs of said first and second OR gates are opposite one another.

Claim 7

The semiconductor device of claim 1, wherein said test pattern generating circuit means comprises: at least a first and a second pair of AND gates; and an exclusive NOR gate receiving an input from a least significant bit signal of column address signals from said part of said address signals and another input from a least significant bit signal of row address signals from said part of said address signals, wherein a first AND gate of said first pair receives one input from said control signal, and a second input from the output of said exclusive NOR gate, and wherein a second AND gate of said first pair receives one input from an inverted signal of said control signal, and a second input from an inverted signal from the output of said exclusive NOR gate, and wherein a first AND gate of said second pair receives one input from said inverted control signal and a second input from said inverted signal from the output of said exclusive NOR gate, and wherein a second AND gate of said second pair recevies one input from said control signal and a second input from the output of said exclusive NOR gate, and wherein the outputs of said first pair of AND gates are input to a first OR gate, and the outputs of said second pair of AND gates are input to a second OR gate, the outputs of said first and second OR gates being connected to said selector, such that upon the providing of said control signal, the outputs of said first and second OR gates are the same.