Abstract Test circuitry is disclosed for testing a circuit module with a high probability of error detection. The circuitry is relatively simple and is therefore readily adaptable for integration with the module to be tested thereby providing effective fault detection capability at the system level. A pseudo-random pattern generator provides the logic to be tested with a series of parallel test inputs. The output from the logic at the end of each cycle within the test sequence is multiplexed into a sequential bit stream which forms the input to a cyclic code generator. After the test sequence has been run for a predetermined number of cycles, the output of the cyclic code generator is compared with a hardwired constant representative of the output of a good unit. Inasmuch as the cyclic code generator is not reset between cycles, two levels of output data reduction are provided - within a single test cycle and within a sequence of cycles. If the comparison indicates a mismatch, an error signal is output.
Test circuitry adaptable for integration with a circuit having a M-bit input and N-bit output to be tested, said test circuitry and said circuit forming a single replaceable unit within a larger hardware system and comprising: means for providing a predetermined sequence of T-Test patterns, each of M-bits for application to said M-bit input; a parallel to serial multiplexer for converting the M-bits of circuit output to a single serial bit stream; a cyclic code generator responsive to the serial output of said multiplexer for encoding a single K-bit number representative of T successive N-bit output patterns from said circuit, K being equal to or greater than 4 and less than T times N; a hardwired constant representative of the output from a good circuit; and a comparator for comparing said K-bit number with said hardwired constant.
Claim 2
Dependent Claim
137 words
Test circuitry adaptable for integration with a circuit having a M-bit input and N-bit output to be tested, said test circuitry and said circuit forming a single replaceable unit within a larger hardware system and comprising: means for providing a predetermined sequence of T-Test patterns, each of M-bits for application to said M-bit input; a parallel to serial multiplexer for converting the M-bits of circuit output to a single serial bit stream; a cyclic code generator responsive to the serial output of said multiplexer for encoding a single K-bit number representative of T successive N-bit output patterns from said circuit, K being equal to or greater than 4 and less than T times N; a hardwired constant representative of the output from a good circuit; and a comparator for comparing said K-bit number with said hardwired constant.