Addressing modes for a dynamic single bit per cell to multiple bit per cell memory

Claim 1

A memory system comprising: a plurality of memory cells, each memory cell capable of storing any one of at least 2 n threshold levels, wherein the threshold levels designate states corresponding to storage of "n" bits of data; an address buffer coupled to the memory cells for generating a plurality of physical addresses such that each physical address uniquely identifies "j" of the memory cells, wherein the "j" memory cells are associated with at least one memory location for storing data; a switch control for selecting one of a standard cell mode and a multi-level cell (MLC) mode of operation; a select circuit coupled to the switch control and the plurality of memory cells for accessing one bit per memory cell when operating in a standard cell mode, and for accessing more than one bit per memory cell when operating in a multi-level cell (MLC) mode, wherein the memory system exhibits an n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, wherein the memory system exhibits a 1:1 correspondence between memory locations and the physical addresses when operating in the standard cell mode; an MLC address register for storing an MLC address, wherein the MLC address identifies a portion of data associated with a given physical address when operating in the MLC mode; a program controller coupled to said switch control for programming control structure data in said standard cell mode, and for programming data structures in said MLC mode.

Claim 12

A method of storing data comprising the steps of: storing one of at least 2 n threshold levels in a subset of a plurality of memory cells, wherein said threshold levels designate states corresponding to storage of "n" bits of data for each memory cell within said subset; selecting an operating mode including at least one of a multi-level cell (MLC) mode and a standard cell mode, wherein said MLC mode specifies storing more than one bit of data for each memory cell and said standard cell mode specifies storing one bit of data for each memory cell; storing an MLC address from a command into an MLC address register, wherein said MLC address identifies a portion of data associated with a given physical address when operating in said MLC mode; generating a plurality of physical addresses in response to an input address, wherein each physical address uniquely identifies "j" memory cells, wherein one bit per memory cell is accessed to exhibit a 1:1 correspondence between memory locations and said physical addresses when operating in said standard cell mode, wherein more than one bit per memory cell is accessed to exhibit an n:1 correspondence between memory locations and physical addresses when operating in said MLC mode; programming control structure data in said standard cell mode; and programming data structures in said MLC mode, wherein the plurality of memory cells contain said control structure data and said data structures.

Claim 13

A method of storing data comprising the steps of: storing one of at least 2 n threshold levels in a subset of a plurality of memory cells, wherein said threshold levels designate states corresponding to storage of "n" bits of data for each memory cell within said subset; selecting an operating mode including at least one of a multi-level cell (MLC) mode and a standard cell mode, wherein said MLC mode specifies storing more than one bit of data for each memory cell and said standard cell mode specifies storing one bit of data for each memory cell; storing an MLC address from a command into an MLC address register, wherein said MLC address identifies a portion of data associated with a given physical address when operating in said MLC mode; generating a plurality of physical addresses in response to an input address, wherein each physical address uniquely identifies "j" memory cells, wherein one bit per memory cell is accessed to exhibit a 1:1 correspondence between memory locations and said physical addresses when operating in said standard cell mode, wherein more than one bit per memory cell is accessed to exhibit an n:1 correspondence between memory locations and physical addresses when operating in said MLC mode; programming control structure data in said standard cell mode; and programming data structures in said MLC mode, wherein the plurality of memory cells contain said control structure data and said data structures.